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Re: [PATCH v1 01/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v1 01/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU |
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Date: |
Mon, 26 Oct 2020 16:55:45 +0800 |
On Fri, Oct 23, 2020 at 11:44 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
- [PATCH v1 00/16] RISC-V: Start to remove xlen preprocess, Alistair Francis, 2020/10/23
- [PATCH v1 01/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, Alistair Francis, 2020/10/23
- Re: [PATCH v1 01/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU,
Bin Meng <=
- [PATCH v1 02/16] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/10/23
- [PATCH v1 03/16] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/10/23
- [PATCH v1 04/16] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/10/23
- [PATCH v1 05/16] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/10/23
- [PATCH v1 06/16] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/10/23