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[PATCH v1 01/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
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From: |
Alistair Francis |
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Subject: |
[PATCH v1 01/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU |
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Date: |
Fri, 23 Oct 2020 08:33:16 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index de4705bb57..74a236d4bc 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -44,6 +44,12 @@
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
+#if defined(TARGET_RISCV32)
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
+#elif defined(TARGET_RISCV64)
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
+#endif
+
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
--
2.28.0
- [PATCH v1 00/16] RISC-V: Start to remove xlen preprocess, Alistair Francis, 2020/10/23
- [PATCH v1 01/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU,
Alistair Francis <=
- [PATCH v1 02/16] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/10/23
- [PATCH v1 03/16] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/10/23
- [PATCH v1 04/16] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/10/23
- [PATCH v1 05/16] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/10/23
- [PATCH v1 06/16] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/10/23