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Re: [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64 |
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Date: |
Fri, 31 Jul 2020 10:25:12 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
> + if (env->misa & RVV) {
> + /* TODO: support vlen other than 128, 256, 512 bits. */
> + const char *vector_xml_name = NULL;
> + switch (cpu->cfg.vlen) {
> + case 128:
> + vector_xml_name = "riscv-64bit-vector-128b.xml";
> + break;
> + case 256:
> + vector_xml_name = "riscv-64bit-vector-256b.xml";
> + break;
> + case 512:
> + vector_xml_name = "riscv-64bit-vector-512b.xml";
> + break;
> + default:
> + vector_xml_name = NULL;
> + break;
> + }
I guess this is ok as-is, but consider mirroring arm_gen_dynamic_svereg_xml().
r~
- [RFC v2 68/76] fpu: add api to handle alternative sNaN propagation, (continued)
- [RFC v2 68/76] fpu: add api to handle alternative sNaN propagation, frank . chang, 2020/07/22
- [RFC v2 69/76] target/riscv: rvv-0.9: floating-point min/max instructions, frank . chang, 2020/07/22
- [RFC v2 70/76] softfloat: add fp16 and uint8/int8 interconvert functions, frank . chang, 2020/07/22
- [RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert, frank . chang, 2020/07/22
- [RFC v2 72/76] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert, frank . chang, 2020/07/22
- [RFC v2 73/76] fpu: fix float16 nan check, frank . chang, 2020/07/22
- [RFC v2 74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2020/07/22
- [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64, frank . chang, 2020/07/22
- Re: [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64,
Richard Henderson <=
- [RFC v2 76/76] target/riscv: gdb: support vector registers for rv32, frank . chang, 2020/07/22