[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC v2 73/76] fpu: fix float16 nan check
From: |
frank . chang |
Subject: |
[RFC v2 73/76] fpu: fix float16 nan check |
Date: |
Wed, 22 Jul 2020 17:16:36 +0800 |
From: Chih-Min Chao <chihmin.chao@sifive.com>
16 15 10 0
|sign | exp | mantissa |
qNaN x 11111 1x_xxxx_xxxx
The mask should check exp + msb of mantissa
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat-specialize.inc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c
index 44f5b661f8..fe7a5e79e4 100644
--- a/fpu/softfloat-specialize.inc.c
+++ b/fpu/softfloat-specialize.inc.c
@@ -254,7 +254,7 @@ bool float16_is_quiet_nan(float16 a_, float_status *status)
if (snan_bit_is_one(status)) {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
} else {
- return ((a & ~0x8000) >= 0x7C80);
+ return ((a & ~0x8000) >= 0x7E00);
}
#endif
}
@@ -271,7 +271,7 @@ bool float16_is_signaling_nan(float16 a_, float_status
*status)
#else
uint16_t a = float16_val(a_);
if (snan_bit_is_one(status)) {
- return ((a & ~0x8000) >= 0x7C80);
+ return ((a & ~0x8000) >= 0x7E00);
} else {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
}
--
2.17.1
- Re: [RFC v2 66/76] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf, (continued)
- [RFC v2 67/76] target/riscv: rvv-0.9: remove integer extract instruction, frank . chang, 2020/07/22
- [RFC v2 68/76] fpu: add api to handle alternative sNaN propagation, frank . chang, 2020/07/22
- [RFC v2 69/76] target/riscv: rvv-0.9: floating-point min/max instructions, frank . chang, 2020/07/22
- [RFC v2 70/76] softfloat: add fp16 and uint8/int8 interconvert functions, frank . chang, 2020/07/22
- [RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert, frank . chang, 2020/07/22
- [RFC v2 72/76] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert, frank . chang, 2020/07/22
- [RFC v2 73/76] fpu: fix float16 nan check,
frank . chang <=
- [RFC v2 74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2020/07/22
- [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64, frank . chang, 2020/07/22
- [RFC v2 76/76] target/riscv: gdb: support vector registers for rv32, frank . chang, 2020/07/22