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Re: [PULL 0/7] target-arm queue
From: |
Peter Maydell |
Subject: |
Re: [PULL 0/7] target-arm queue |
Date: |
Tue, 28 Jul 2020 19:43:10 +0100 |
On Mon, 27 Jul 2020 at 16:19, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Just some bugfixes this time around.
>
> -- PMM
>
> The following changes since commit 4215d3413272ad6d1c6c9d0234450b602e46a74c:
>
> Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200727'
> into staging (2020-07-27 09:33:04 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20200727
>
> for you to fetch changes up to d4f6dda182e19afa75706936805e18397cb95f07:
>
> target/arm: Improve IMPDEF algorithm for IRG (2020-07-27 16:12:11 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * ACPI: Assert that we don't run out of the preallocated memory
> * hw/misc/aspeed_sdmc: Fix incorrect memory size
> * target/arm: Always pass cacheattr in S1_ptw_translate
> * docs/system/arm/virt: Document 'mte' machine option
> * hw/arm/boot: Fix PAUTH, MTE for EL3 direct kernel boot
> * target/arm: Improve IMPDEF algorithm for IRG
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.
-- PMM
- [PULL 0/7] target-arm queue, Peter Maydell, 2020/07/27
- [PULL 2/7] hw/misc/aspeed_sdmc: Fix incorrect memory size, Peter Maydell, 2020/07/27
- [PULL 3/7] target/arm: Always pass cacheattr in S1_ptw_translate, Peter Maydell, 2020/07/27
- [PULL 1/7] ACPI: Assert that we don't run out of the preallocated memory, Peter Maydell, 2020/07/27
- [PULL 4/7] docs/system/arm/virt: Document 'mte' machine option, Peter Maydell, 2020/07/27
- [PULL 5/7] hw/arm/boot: Fix PAUTH for EL3 direct kernel boot, Peter Maydell, 2020/07/27
- [PULL 6/7] hw/arm/boot: Fix MTE for EL3 direct kernel boot, Peter Maydell, 2020/07/27
- [PULL 7/7] target/arm: Improve IMPDEF algorithm for IRG, Peter Maydell, 2020/07/27
- Re: [PULL 0/7] target-arm queue,
Peter Maydell <=