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[PULL 3/7] target/arm: Always pass cacheattr in S1_ptw_translate
From: |
Peter Maydell |
Subject: |
[PULL 3/7] target/arm: Always pass cacheattr in S1_ptw_translate |
Date: |
Mon, 27 Jul 2020 16:19:16 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
When we changed the interface of get_phys_addr_lpae to require
the cacheattr parameter, this spot was missed. The compiler is
unable to detect the use of NULL vs the nonnull attribute here.
Fixes: 7e98e21c098
Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Jan Kiszka <jan.kiskza@siemens.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 19 ++++++-------------
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c69a2baf1d3..8ef0fb478f4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10204,21 +10204,11 @@ static hwaddr S1_ptw_translate(CPUARMState *env,
ARMMMUIdx mmu_idx,
int s2prot;
int ret;
ARMCacheAttrs cacheattrs = {};
- ARMCacheAttrs *pcacheattrs = NULL;
-
- if (env->cp15.hcr_el2 & HCR_PTW) {
- /*
- * PTW means we must fault if this S1 walk touches S2 Device
- * memory; otherwise we don't care about the attributes and can
- * save the S2 translation the effort of computing them.
- */
- pcacheattrs = &cacheattrs;
- }
ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
false,
&s2pa, &txattrs, &s2prot, &s2size, fi,
- pcacheattrs);
+ &cacheattrs);
if (ret) {
assert(fi->type != ARMFault_None);
fi->s2addr = addr;
@@ -10226,8 +10216,11 @@ static hwaddr S1_ptw_translate(CPUARMState *env,
ARMMMUIdx mmu_idx,
fi->s1ptw = true;
return ~0;
}
- if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) {
- /* Access was to Device memory: generate Permission fault */
+ if ((env->cp15.hcr_el2 & HCR_PTW) && (cacheattrs.attrs & 0xf0) == 0) {
+ /*
+ * PTW set and S1 walk touched S2 Device memory:
+ * generate Permission fault.
+ */
fi->type = ARMFault_Permission;
fi->s2addr = addr;
fi->stage2 = true;
--
2.20.1
- [PULL 0/7] target-arm queue, Peter Maydell, 2020/07/27
- [PULL 2/7] hw/misc/aspeed_sdmc: Fix incorrect memory size, Peter Maydell, 2020/07/27
- [PULL 3/7] target/arm: Always pass cacheattr in S1_ptw_translate,
Peter Maydell <=
- [PULL 1/7] ACPI: Assert that we don't run out of the preallocated memory, Peter Maydell, 2020/07/27
- [PULL 4/7] docs/system/arm/virt: Document 'mte' machine option, Peter Maydell, 2020/07/27
- [PULL 5/7] hw/arm/boot: Fix PAUTH for EL3 direct kernel boot, Peter Maydell, 2020/07/27
- [PULL 6/7] hw/arm/boot: Fix MTE for EL3 direct kernel boot, Peter Maydell, 2020/07/27
- [PULL 7/7] target/arm: Improve IMPDEF algorithm for IRG, Peter Maydell, 2020/07/27
- Re: [PULL 0/7] target-arm queue, Peter Maydell, 2020/07/28