[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 15/32] target/avr: Add instruction translation - MCU Control Instr
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 15/32] target/avr: Add instruction translation - MCU Control Instructions |
Date: |
Tue, 7 Jul 2020 20:16:53 +0200 |
From: Michael Rolnik <mrolnik@gmail.com>
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-16-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/avr/insn.decode | 8 ++++++
target/avr/translate.c | 65 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 73 insertions(+)
diff --git a/target/avr/insn.decode b/target/avr/insn.decode
index 7bb6ce7495..482c23ad0c 100644
--- a/target/avr/insn.decode
+++ b/target/avr/insn.decode
@@ -177,3 +177,11 @@ BST 1111 101 rd:5 0 bit:3
BLD 1111 100 rd:5 0 bit:3
BSET 1001 0100 0 bit:3 1000
BCLR 1001 0100 1 bit:3 1000
+
+#
+# MCU Control Instructions
+#
+BREAK 1001 0101 1001 1000
+NOP 0000 0000 0000 0000
+SLEEP 1001 0101 1000 1000
+WDR 1001 0101 1010 1000
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 884fbb6081..ee7811995a 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2740,3 +2740,68 @@ static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a)
return true;
}
+
+/*
+ * MCU Control Instructions
+ */
+
+/*
+ * The BREAK instruction is used by the On-chip Debug system, and is
+ * normally not used in the application software. When the BREAK instruction
is
+ * executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip
+ * Debugger access to internal resources. If any Lock bits are set, or either
+ * the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK
+ * instruction as a NOP and will not enter the Stopped mode. This instruction
+ * is not available in all devices. Refer to the device specific instruction
+ * set summary.
+ */
+static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)
+{
+ if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) {
+ return true;
+ }
+
+#ifdef BREAKPOINT_ON_BREAK
+ tcg_gen_movi_tl(cpu_pc, ctx->npc - 1);
+ gen_helper_debug(cpu_env);
+ ctx->bstate = DISAS_EXIT;
+#else
+ /* NOP */
+#endif
+
+ return true;
+}
+
+/*
+ * This instruction performs a single cycle No Operation.
+ */
+static bool trans_NOP(DisasContext *ctx, arg_NOP *a)
+{
+
+ /* NOP */
+
+ return true;
+}
+
+/*
+ * This instruction sets the circuit in sleep mode defined by the MCU
+ * Control Register.
+ */
+static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a)
+{
+ gen_helper_sleep(cpu_env);
+ ctx->bstate = DISAS_NORETURN;
+ return true;
+}
+
+/*
+ * This instruction resets the Watchdog Timer. This instruction must be
+ * executed within a limited time given by the WD prescaler. See the Watchdog
+ * Timer hardware specification.
+ */
+static bool trans_WDR(DisasContext *ctx, arg_WDR *a)
+{
+ gen_helper_wdr(cpu_env);
+
+ return true;
+}
--
2.21.3
- [PULL 04/32] target/avr: CPU class: Add memory menagement support, (continued)
- [PULL 04/32] target/avr: CPU class: Add memory menagement support, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 05/32] target/avr: CPU class: Add migration support, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 06/32] target/avr: CPU class: Add GDB support, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 07/32] target/avr: Introduce enumeration AVRFeature, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 08/32] target/avr: Add definitions of AVR core types, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 09/32] target/avr: Add instruction helpers, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 10/32] target/avr: Add instruction translation - Register definitions, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 11/32] target/avr: Add instruction translation - Arithmetic and Logic Instructions, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 12/32] target/avr: Add instruction translation - Branch Instructions, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 13/32] target/avr: Add instruction translation - Data Transfer Instructions, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 15/32] target/avr: Add instruction translation - MCU Control Instructions,
Philippe Mathieu-Daudé <=
- [PULL 14/32] target/avr: Add instruction translation - Bit and Bit-test Instructions, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 17/32] target/avr: Initialize TCG register variables, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 16/32] target/avr: Add instruction translation - CPU main translation function, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 18/32] target/avr: Add support for disassembling via option '-d in_asm', Philippe Mathieu-Daudé, 2020/07/07
- [PULL 19/32] target/avr: Register AVR support with the rest of QEMU, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 20/32] tests/machine-none: Add AVR support, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 21/32] hw/char: avr: Add limited support for USART peripheral, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 22/32] hw/timer: avr: Add limited support for 16-bit timer peripheral, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 26/32] hw/avr: Add limited support for some Arduino boards, Philippe Mathieu-Daudé, 2020/07/07
- [PULL 24/32] hw/avr: Add support for loading ELF/raw binaries, Philippe Mathieu-Daudé, 2020/07/07