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[PATCH rc6 15/30] target/avr: Add instruction translation - MCU Control
From: |
Thomas Huth |
Subject: |
[PATCH rc6 15/30] target/avr: Add instruction translation - MCU Control Instructions |
Date: |
Sun, 5 Jul 2020 16:03:00 +0200 |
From: Michael Rolnik <mrolnik@gmail.com>
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
---
target/avr/insn.decode | 8 +++++
target/avr/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 76 insertions(+)
diff --git a/target/avr/insn.decode b/target/avr/insn.decode
index 8141e180d2..0220da2593 100644
--- a/target/avr/insn.decode
+++ b/target/avr/insn.decode
@@ -177,3 +177,11 @@ BST 1111 101 rd:5 0 bit:3
BLD 1111 100 rd:5 0 bit:3
BSET 1001 0100 0 bit:3 1000
BCLR 1001 0100 1 bit:3 1000
+
+#
+# MCU Control Instructions
+#
+BREAK 1001 0101 1001 1000
+NOP 0000 0000 0000 0000
+SLEEP 1001 0101 1000 1000
+WDR 1001 0101 1010 1000
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 315f534f66..806a0f4e78 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2747,3 +2747,71 @@ static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a)
return true;
}
+
+/*
+ * MCU Control Instructions
+ */
+
+/*
+ * The BREAK instruction is used by the On-chip Debug system, and is
+ * normally not used in the application software. When the BREAK instruction
is
+ * executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip
+ * Debugger access to internal resources. If any Lock bits are set, or either
+ * the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK
+ * instruction as a NOP and will not enter the Stopped mode. This instruction
+ * is not available in all devices. Refer to the device specific instruction
+ * set summary.
+ */
+static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)
+{
+ if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) {
+ return true;
+ }
+
+#ifdef BREAKPOINT_ON_BREAK
+ tcg_gen_movi_tl(cpu_pc, ctx->npc - 1);
+ gen_helper_debug(cpu_env);
+ ctx->bstate = DISAS_EXIT;
+#else
+ /* NOP */
+#endif
+
+ return true;
+}
+
+
+/*
+ * This instruction performs a single cycle No Operation.
+ */
+static bool trans_NOP(DisasContext *ctx, arg_NOP *a)
+{
+
+ /* NOP */
+
+ return true;
+}
+
+
+/*
+ * This instruction sets the circuit in sleep mode defined by the MCU
+ * Control Register.
+ */
+static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a)
+{
+ gen_helper_sleep(cpu_env);
+ ctx->bstate = DISAS_NORETURN;
+ return true;
+}
+
+
+/*
+ * This instruction resets the Watchdog Timer. This instruction must be
+ * executed within a limited time given by the WD prescaler. See the Watchdog
+ * Timer hardware specification.
+ */
+static bool trans_WDR(DisasContext *ctx, arg_WDR *a)
+{
+ gen_helper_wdr(cpu_env);
+
+ return true;
+}
--
2.26.2
- [PATCH rc6 06/30] target/avr: CPU class: Add GDB support, (continued)
- [PATCH rc6 06/30] target/avr: CPU class: Add GDB support, Thomas Huth, 2020/07/05
- [PATCH rc6 08/30] target/avr: Add defintions of AVR core types, Thomas Huth, 2020/07/05
- [PATCH rc6 09/30] target/avr: Add instruction helpers, Thomas Huth, 2020/07/05
- [PATCH rc6 07/30] target/avr: Introduce enumeration AVRFeature, Thomas Huth, 2020/07/05
- [PATCH rc6 10/30] target/avr: Add instruction translation - Register definitions, Thomas Huth, 2020/07/05
- [PATCH rc6 11/30] target/avr: Add instruction translation - Arithmetic and Logic Instructions, Thomas Huth, 2020/07/05
- [PATCH rc6 14/30] target/avr: Add instruction translation - Bit and Bit-test Instructions, Thomas Huth, 2020/07/05
- [PATCH rc6 17/30] target/avr: Initialize TCG register variables, Thomas Huth, 2020/07/05
- [PATCH rc6 13/30] target/avr: Add instruction translation - Data Transfer Instructions, Thomas Huth, 2020/07/05
- [PATCH rc6 12/30] target/avr: Add instruction translation - Branch Instructions, Thomas Huth, 2020/07/05
- [PATCH rc6 15/30] target/avr: Add instruction translation - MCU Control Instructions,
Thomas Huth <=
- [PATCH rc6 16/30] target/avr: Add instruction translation - CPU main translation function, Thomas Huth, 2020/07/05
- [PATCH rc6 18/30] target/avr: Add support for disassembling via option '-d in_asm', Thomas Huth, 2020/07/05
- [PATCH rc6 19/30] hw/char: avr: Add limited support for USART peripheral, Thomas Huth, 2020/07/05
- [PATCH rc6 21/30] hw/misc: avr: Add limited support for power reduction device, Thomas Huth, 2020/07/05
- [PATCH rc6 20/30] hw/timer: avr: Add limited support for 16-bit timer peripheral, Thomas Huth, 2020/07/05
- [PATCH rc6 22/30] target/avr: Register AVR support with the rest of QEMU, Thomas Huth, 2020/07/05
- [PATCH rc6 26/30] target/avr: Update build system, Thomas Huth, 2020/07/05