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[PATCH v8 14/45] target/arm: Define arm_cpu_do_unaligned_access for user
From: |
Richard Henderson |
Subject: |
[PATCH v8 14/45] target/arm: Define arm_cpu_do_unaligned_access for user-only |
Date: |
Tue, 23 Jun 2020 12:36:27 -0700 |
Use the same code as system mode, so that we generate the same
exception + syndrome for the unaligned access.
For the moment, if MTE is enabled so that this path is reachable,
this would generate a SIGSEGV in the user-only cpu_loop. Decoding
the syndrome to produce the proper SIGBUS will be done later.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v8: Raise the normal data exception + syndrome.
---
target/arm/cpu.c | 2 +-
target/arm/tlb_helper.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5b7a36b5d7..10677c0c23 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2169,8 +2169,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
cc->tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
-#if !defined(CONFIG_USER_ONLY)
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
+#if !defined(CONFIG_USER_ONLY)
cc->do_transaction_failed = arm_cpu_do_transaction_failed;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 7388494a55..522a6442a4 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -10,8 +10,6 @@
#include "internals.h"
#include "exec/exec-all.h"
-#if !defined(CONFIG_USER_ONLY)
-
static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
unsigned int target_el,
bool same_el, bool ea,
@@ -122,6 +120,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
}
+#if !defined(CONFIG_USER_ONLY)
+
/*
* arm_cpu_do_transaction_failed: handle a memory system error response
* (eg "no device/memory present at address") by raising an external abort
--
2.25.1
- [PATCH v8 06/45] target/arm: Add DISAS_UPDATE_NOCHAIN, (continued)
- [PATCH v8 06/45] target/arm: Add DISAS_UPDATE_NOCHAIN, Richard Henderson, 2020/06/23
- [PATCH v8 07/45] target/arm: Add MTE system registers, Richard Henderson, 2020/06/23
- [PATCH v8 08/45] target/arm: Add MTE bits to tb_flags, Richard Henderson, 2020/06/23
- [PATCH v8 09/45] target/arm: Implement the IRG instruction, Richard Henderson, 2020/06/23
- [PATCH v8 10/45] target/arm: Revise decoding for disas_add_sub_imm, Richard Henderson, 2020/06/23
- [PATCH v8 11/45] target/arm: Implement the ADDG, SUBG instructions, Richard Henderson, 2020/06/23
- [PATCH v8 12/45] target/arm: Implement the GMI instruction, Richard Henderson, 2020/06/23
- [PATCH v8 13/45] target/arm: Implement the SUBP instruction, Richard Henderson, 2020/06/23
- [PATCH v8 14/45] target/arm: Define arm_cpu_do_unaligned_access for user-only,
Richard Henderson <=
- [PATCH v8 16/45] target/arm: Implement the STGP instruction, Richard Henderson, 2020/06/23
- [PATCH v8 15/45] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2020/06/23
- [PATCH v8 18/45] target/arm: Simplify DC_ZVA, Richard Henderson, 2020/06/23
- [PATCH v8 17/45] target/arm: Restrict the values of DCZID.BS under TCG, Richard Henderson, 2020/06/23
- [PATCH v8 19/45] target/arm: Implement the LDGM, STGM, STZGM instructions, Richard Henderson, 2020/06/23
- [PATCH v8 20/45] target/arm: Implement the access tag cache flushes, Richard Henderson, 2020/06/23
- [PATCH v8 21/45] target/arm: Move regime_el to internals.h, Richard Henderson, 2020/06/23
- [PATCH v8 22/45] target/arm: Move regime_tcr to internals.h, Richard Henderson, 2020/06/23