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[PULL v2 26/32] hw/riscv: sifive_u: Rename serial property get/set funct
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From: |
Alistair Francis |
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Subject: |
[PULL v2 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name |
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Date: |
Fri, 19 Jun 2020 09:58:11 -0700 |
From: Bin Meng <bin.meng@windriver.com>
In prepration to add more properties to this machine, rename the
existing serial property get/set functions to a generic name.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-11-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-11-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b9d2185c04..6dac662910 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -478,14 +478,16 @@ static void sifive_u_machine_set_start_in_flash(Object
*obj, bool value, Error *
s->start_in_flash = value;
}
-static void sifive_u_machine_get_serial(Object *obj, Visitor *v, const char
*name,
- void *opaque, Error **errp)
+static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
{
visit_type_uint32(v, name, (uint32_t *)opaque, errp);
}
-static void sifive_u_machine_set_serial(Object *obj, Visitor *v, const char
*name,
- void *opaque, Error **errp)
+static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
{
visit_type_uint32(v, name, (uint32_t *)opaque, errp);
}
@@ -504,8 +506,8 @@ static void sifive_u_machine_instance_init(Object *obj)
s->serial = OTP_SERIAL;
object_property_add(obj, "serial", "uint32",
- sifive_u_machine_get_serial,
- sifive_u_machine_set_serial, NULL, &s->serial);
+ sifive_u_machine_get_uint32_prop,
+ sifive_u_machine_set_uint32_prop, NULL, &s->serial);
object_property_set_description(obj, "serial", "Board serial number");
}
--
2.27.0
- [PULL v2 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs, (continued)
- [PULL v2 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs, Alistair Francis, 2020/06/19
- [PULL v2 18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL v2 20/32] hw/riscv: sifive_u: Generate device tree node for OTP, Alistair Francis, 2020/06/19
- [PULL v2 23/32] hw/riscv: sifive_u: Hook a GPIO controller, Alistair Francis, 2020/06/19
- [PULL v2 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/06/19
- [PULL v2 10/32] target/riscv: Implement checks for hfence, Alistair Francis, 2020/06/19
- [PULL v2 11/32] riscv/opentitan: Fix the ROM size, Alistair Francis, 2020/06/19
- [PULL v2 09/32] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/19
- [PULL v2 12/32] hw/char: Initial commit of Ibex UART, Alistair Francis, 2020/06/19
- [PULL v2 25/32] hw/riscv: sifive_u: Add reset functionality, Alistair Francis, 2020/06/19
- [PULL v2 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name,
Alistair Francis <=
- [PULL v2 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state, Alistair Francis, 2020/06/19
- [PULL v2 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/06/19
- [PULL v2 28/32] target/riscv: Rename IBEX CPU init routine, Alistair Francis, 2020/06/19
- [PULL v2 29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004, Alistair Francis, 2020/06/19
- [PULL v2 30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state, Alistair Francis, 2020/06/19
- [PULL v2 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries, Alistair Francis, 2020/06/19
- [PULL v2 32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device, Alistair Francis, 2020/06/19
- Re: [PULL v2 00/32] riscv-to-apply queue, no-reply, 2020/06/19
- Re: [PULL v2 00/32] riscv-to-apply queue, Peter Maydell, 2020/06/22