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[PULL v2 25/32] hw/riscv: sifive_u: Add reset functionality
From: |
Alistair Francis |
Subject: |
[PULL v2 25/32] hw/riscv: sifive_u: Add reset functionality |
Date: |
Fri, 19 Jun 2020 09:58:10 -0700 |
From: Bin Meng <bin.meng@windriver.com>
The HiFive Unleashed board wires GPIO pin#10 to the input of the
system reset signal. Let's set up the GPIO pin#10 and insert a
"gpio-restart" device tree node so that reboot is now functional
with QEMU 'sifive_u' machine.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-10-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f6976a0d09..b9d2185c04 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -37,6 +37,7 @@
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "hw/boards.h"
+#include "hw/irq.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
@@ -53,6 +54,7 @@
#include "net/eth.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
+#include "sysemu/runstate.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
@@ -96,7 +98,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
uint32_t *cells;
char *nodename;
char ethclk_names[] = "pclk\0hclk";
- uint32_t plic_phandle, prci_phandle, phandle = 1;
+ uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
fdt = s->fdt = create_device_tree(&s->fdt_size);
@@ -270,9 +272,11 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
+ gpio_phandle = phandle++;
nodename = g_strdup_printf("/soc/gpio@%lx",
(long)memmap[SIFIVE_U_GPIO].base);
qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
prci_phandle, PRCI_CLK_TLCLK);
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
@@ -292,6 +296,12 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
g_free(nodename);
+ nodename = g_strdup_printf("/gpio-restart");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
+ g_free(nodename);
+
phy_phandle = phandle++;
nodename = g_strdup_printf("/soc/ethernet@%lx",
(long)memmap[SIFIVE_U_GEM].base);
@@ -352,6 +362,14 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
g_free(nodename);
}
+static void sifive_u_machine_reset(void *opaque, int n, int level)
+{
+ /* gpio pin active low triggers reset */
+ if (!level) {
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ }
+}
+
static void sifive_u_machine_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_u_memmap;
@@ -380,6 +398,10 @@ static void sifive_u_machine_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
flash0);
+ /* register gpio-restart */
+ qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
+ qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
+
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
--
2.27.0
- [PULL v2 21/32] hw/riscv: sifive_gpio: Clean up the codes, (continued)
- [PULL v2 21/32] hw/riscv: sifive_gpio: Clean up the codes, Alistair Francis, 2020/06/19
- [PULL v2 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs, Alistair Francis, 2020/06/19
- [PULL v2 18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL v2 20/32] hw/riscv: sifive_u: Generate device tree node for OTP, Alistair Francis, 2020/06/19
- [PULL v2 23/32] hw/riscv: sifive_u: Hook a GPIO controller, Alistair Francis, 2020/06/19
- [PULL v2 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/06/19
- [PULL v2 10/32] target/riscv: Implement checks for hfence, Alistair Francis, 2020/06/19
- [PULL v2 11/32] riscv/opentitan: Fix the ROM size, Alistair Francis, 2020/06/19
- [PULL v2 09/32] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/19
- [PULL v2 12/32] hw/char: Initial commit of Ibex UART, Alistair Francis, 2020/06/19
- [PULL v2 25/32] hw/riscv: sifive_u: Add reset functionality,
Alistair Francis <=
- [PULL v2 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name, Alistair Francis, 2020/06/19
- [PULL v2 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state, Alistair Francis, 2020/06/19
- [PULL v2 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/06/19
- [PULL v2 28/32] target/riscv: Rename IBEX CPU init routine, Alistair Francis, 2020/06/19
- [PULL v2 29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004, Alistair Francis, 2020/06/19
- [PULL v2 30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state, Alistair Francis, 2020/06/19
- [PULL v2 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries, Alistair Francis, 2020/06/19
- [PULL v2 32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device, Alistair Francis, 2020/06/19
- Re: [PULL v2 00/32] riscv-to-apply queue, no-reply, 2020/06/19
- Re: [PULL v2 00/32] riscv-to-apply queue, Peter Maydell, 2020/06/22