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[PULL 11/32] riscv/opentitan: Fix the ROM size
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From: |
Alistair Francis |
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Subject: |
[PULL 11/32] riscv/opentitan: Fix the ROM size |
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Date: |
Thu, 18 Jun 2020 23:24:57 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Damien Hedde <damien.hedde@greensocs.com>
---
hw/riscv/opentitan.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index f6776da8e9..011e4f7ee2 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -25,12 +25,13 @@
#include "hw/misc/unimp.h"
#include "hw/riscv/boot.h"
#include "exec/address-spaces.h"
+#include "qemu/units.h"
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} ibex_memmap[] = {
- [IBEX_ROM] = { 0x00008000, 0xc000 },
+ [IBEX_ROM] = { 0x00008000, 16 * KiB },
[IBEX_RAM] = { 0x10000000, 0x10000 },
[IBEX_FLASH] = { 0x20000000, 0x80000 },
[IBEX_UART] = { 0x40000000, 0x10000 },
--
2.27.0
- [PULL 02/32] sifive_e: Support the revB machine, (continued)
- [PULL 02/32] sifive_e: Support the revB machine, Alistair Francis, 2020/06/19
- [PULL 04/32] riscv: Generalize CPU init routine for the gcsu CPU, Alistair Francis, 2020/06/19
- [PULL 18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL 16/32] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/06/19
- [PULL 14/32] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/06/19
- [PULL 06/32] riscv: Keep the CPU init routine names consistent, Alistair Francis, 2020/06/19
- [PULL 21/32] hw/riscv: sifive_gpio: Clean up the codes, Alistair Francis, 2020/06/19
- [PULL 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/06/19
- [PULL 01/32] riscv: Add helper to make NaN-boxing for FP register, Alistair Francis, 2020/06/19
- [PULL 10/32] target/riscv: Implement checks for hfence, Alistair Francis, 2020/06/19
- [PULL 11/32] riscv/opentitan: Fix the ROM size,
Alistair Francis <=
- [PULL 03/32] riscv: Generalize CPU init routine for the base CPU, Alistair Francis, 2020/06/19
- [PULL 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/06/19
- [PULL 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL 05/32] riscv: Generalize CPU init routine for the imacu CPU, Alistair Francis, 2020/06/19
- [PULL 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit, Alistair Francis, 2020/06/19
- [PULL 08/32] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/19
- [PULL 20/32] hw/riscv: sifive_u: Generate device tree node for OTP, Alistair Francis, 2020/06/19
- [PULL 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property, Alistair Francis, 2020/06/19
- [PULL 09/32] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/19
- [PULL 23/32] hw/riscv: sifive_u: Hook a GPIO controller, Alistair Francis, 2020/06/19