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[PULL 03/32] riscv: Generalize CPU init routine for the base CPU
From: |
Alistair Francis |
Subject: |
[PULL 03/32] riscv: Generalize CPU init routine for the base CPU |
Date: |
Thu, 18 Jun 2020 23:24:49 -0700 |
From: Bin Meng <bin.meng@windriver.com>
There is no need to have two functions that have exactly the same
codes for 32-bit and 64-bit base CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591837729-27486-1-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591837729-27486-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3a6d202d03..81cdea8680 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -126,9 +126,7 @@ static void riscv_any_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
-#if defined(TARGET_RISCV32)
-
-static void riscv_base32_cpu_init(Object *obj)
+static void riscv_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
@@ -136,6 +134,8 @@ static void riscv_base32_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
+#if defined(TARGET_RISCV32)
+
static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -173,14 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
-static void riscv_base64_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- /* We set this in the realise function */
- set_misa(env, 0);
- set_resetvec(env, DEFAULT_RSTVEC);
-}
-
static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -603,13 +595,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
},
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(TARGET_RISCV32)
- DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
#elif defined(TARGET_RISCV64)
- DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
#endif
--
2.27.0
- [PULL 04/32] riscv: Generalize CPU init routine for the gcsu CPU, (continued)
- [PULL 04/32] riscv: Generalize CPU init routine for the gcsu CPU, Alistair Francis, 2020/06/19
- [PULL 18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL 16/32] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/06/19
- [PULL 14/32] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/06/19
- [PULL 06/32] riscv: Keep the CPU init routine names consistent, Alistair Francis, 2020/06/19
- [PULL 21/32] hw/riscv: sifive_gpio: Clean up the codes, Alistair Francis, 2020/06/19
- [PULL 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/06/19
- [PULL 01/32] riscv: Add helper to make NaN-boxing for FP register, Alistair Francis, 2020/06/19
- [PULL 10/32] target/riscv: Implement checks for hfence, Alistair Francis, 2020/06/19
- [PULL 11/32] riscv/opentitan: Fix the ROM size, Alistair Francis, 2020/06/19
- [PULL 03/32] riscv: Generalize CPU init routine for the base CPU,
Alistair Francis <=
- [PULL 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/06/19
- [PULL 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL 05/32] riscv: Generalize CPU init routine for the imacu CPU, Alistair Francis, 2020/06/19
- [PULL 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit, Alistair Francis, 2020/06/19
- [PULL 08/32] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/19
- [PULL 20/32] hw/riscv: sifive_u: Generate device tree node for OTP, Alistair Francis, 2020/06/19
- [PULL 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property, Alistair Francis, 2020/06/19
- [PULL 09/32] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/19
- [PULL 23/32] hw/riscv: sifive_u: Hook a GPIO controller, Alistair Francis, 2020/06/19
- [PULL 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs, Alistair Francis, 2020/06/19