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[PULL 26/34] target/arm: Remove sve_memopidx
From: |
Peter Maydell |
Subject: |
[PULL 26/34] target/arm: Remove sve_memopidx |
Date: |
Mon, 11 May 2020 14:33:57 +0100 |
From: Richard Henderson <address@hidden>
None of the sve helpers use TCGMemOpIdx any longer, so we can
stop passing it.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/internals.h | 5 -----
target/arm/sve_helper.c | 14 +++++++-------
target/arm/translate-sve.c | 17 +++--------------
3 files changed, 10 insertions(+), 26 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index e633aff36ef..a833e3941d3 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -979,11 +979,6 @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu)
}
}
-/* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3.
- * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits.
- */
-#define MEMOPIDX_SHIFT 8
-
/**
* v7m_using_psp: Return true if using process stack pointer
* Return true if the CPU is currently using the process stack
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index f1870aabc2f..116d535fa5f 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -4440,7 +4440,7 @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const
target_ulong addr,
sve_ldst1_host_fn *host_fn,
sve_ldst1_tlb_fn *tlb_fn)
{
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
+ const unsigned rd = simd_data(desc);
const intptr_t reg_max = simd_oprsz(desc);
intptr_t reg_off, reg_last, mem_off;
SVEContLdSt info;
@@ -4696,7 +4696,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const
target_ulong addr,
sve_ldst1_host_fn *host_fn,
sve_ldst1_tlb_fn *tlb_fn)
{
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
+ const unsigned rd = simd_data(desc);
void *vd = &env->vfp.zregs[rd];
const intptr_t reg_max = simd_oprsz(desc);
intptr_t reg_off, mem_off, reg_last;
@@ -4925,7 +4925,7 @@ void sve_stN_r(CPUARMState *env, uint64_t *vg,
target_ulong addr, uint32_t desc,
sve_ldst1_host_fn *host_fn,
sve_ldst1_tlb_fn *tlb_fn)
{
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
+ const unsigned rd = simd_data(desc);
const intptr_t reg_max = simd_oprsz(desc);
intptr_t reg_off, reg_last, mem_off;
SVEContLdSt info;
@@ -5131,9 +5131,9 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg,
void *vm,
sve_ldst1_host_fn *host_fn,
sve_ldst1_tlb_fn *tlb_fn)
{
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
const int mmu_idx = cpu_mmu_index(env, false);
const intptr_t reg_max = simd_oprsz(desc);
+ const int scale = simd_data(desc);
ARMVectorReg scratch;
intptr_t reg_off;
SVEHostPage info, info2;
@@ -5276,10 +5276,10 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t
*vg, void *vm,
sve_ldst1_tlb_fn *tlb_fn)
{
const int mmu_idx = cpu_mmu_index(env, false);
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
+ const intptr_t reg_max = simd_oprsz(desc);
+ const int scale = simd_data(desc);
const int esize = 1 << esz;
const int msize = 1 << msz;
- const intptr_t reg_max = simd_oprsz(desc);
intptr_t reg_off;
SVEHostPage info;
target_ulong addr, in_page;
@@ -5430,9 +5430,9 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg,
void *vm,
sve_ldst1_host_fn *host_fn,
sve_ldst1_tlb_fn *tlb_fn)
{
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
const int mmu_idx = cpu_mmu_index(env, false);
const intptr_t reg_max = simd_oprsz(desc);
+ const int scale = simd_data(desc);
void *host[ARM_MAX_VQ * 4];
intptr_t reg_off, i;
SVEHostPage info, info2;
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 6c8bda4e4cc..36816aafaf6 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4582,11 +4582,6 @@ static const uint8_t dtype_esz[16] = {
3, 2, 1, 3
};
-static TCGMemOpIdx sve_memopidx(DisasContext *s, int dtype)
-{
- return make_memop_idx(s->be_data | dtype_mop[dtype], get_mem_index(s));
-}
-
static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
int dtype, gen_helper_gvec_mem *fn)
{
@@ -4599,9 +4594,7 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg,
TCGv_i64 addr,
* registers as pointers, so encode the regno into the data field.
* For consistency, do this even for LD1.
*/
- desc = sve_memopidx(s, dtype);
- desc |= zt << MEMOPIDX_SHIFT;
- desc = simd_desc(vsz, vsz, desc);
+ desc = simd_desc(vsz, vsz, zt);
t_desc = tcg_const_i32(desc);
t_pg = tcg_temp_new_ptr();
@@ -4833,9 +4826,7 @@ static void do_ldrq(DisasContext *s, int zt, int pg,
TCGv_i64 addr, int msz)
int desc, poff;
/* Load the first quadword using the normal predicated load helpers. */
- desc = sve_memopidx(s, msz_dtype(s, msz));
- desc |= zt << MEMOPIDX_SHIFT;
- desc = simd_desc(16, 16, desc);
+ desc = simd_desc(16, 16, zt);
t_desc = tcg_const_i32(desc);
poff = pred_full_reg_offset(s, pg);
@@ -5064,9 +5055,7 @@ static void do_mem_zpz(DisasContext *s, int zt, int pg,
int zm,
TCGv_i32 t_desc;
int desc;
- desc = sve_memopidx(s, msz_dtype(s, msz));
- desc |= scale << MEMOPIDX_SHIFT;
- desc = simd_desc(vsz, vsz, desc);
+ desc = simd_desc(vsz, vsz, scale);
t_desc = tcg_const_i32(desc);
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
--
2.20.1
- [PULL 14/34] target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn, (continued)
- [PULL 14/34] target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn, Peter Maydell, 2020/05/11
- [PULL 16/34] target/arm: Add sve infrastructure for page lookup, Peter Maydell, 2020/05/11
- [PULL 18/34] target/arm: Use SVEContLdSt in sve_ld1_r, Peter Maydell, 2020/05/11
- [PULL 12/34] accel/tcg: Add probe_access_flags, Peter Maydell, 2020/05/11
- [PULL 17/34] target/arm: Adjust interface of sve_ld1_host_fn, Peter Maydell, 2020/05/11
- [PULL 19/34] target/arm: Handle watchpoints in sve_ld1_r, Peter Maydell, 2020/05/11
- [PULL 20/34] target/arm: Use SVEContLdSt for multi-register contiguous loads, Peter Maydell, 2020/05/11
- [PULL 24/34] target/arm: Reuse sve_probe_page for scatter stores, Peter Maydell, 2020/05/11
- [PULL 23/34] target/arm: Reuse sve_probe_page for gather first-fault loads, Peter Maydell, 2020/05/11
- [PULL 22/34] target/arm: Use SVEContLdSt for contiguous stores, Peter Maydell, 2020/05/11
- [PULL 26/34] target/arm: Remove sve_memopidx,
Peter Maydell <=
- [PULL 21/34] target/arm: Update contiguous first-fault and no-fault loads, Peter Maydell, 2020/05/11
- [PULL 27/34] target/arm/kvm: Inline set_feature() calls, Peter Maydell, 2020/05/11
- [PULL 28/34] target/arm: Make set_feature() available for other files, Peter Maydell, 2020/05/11
- [PULL 29/34] target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[], Peter Maydell, 2020/05/11
- [PULL 30/34] target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs, Peter Maydell, 2020/05/11
- [PULL 25/34] target/arm: Reuse sve_probe_page for gather loads, Peter Maydell, 2020/05/11
- [PULL 32/34] hw/arm/musicpal: Map the UART devices unconditionally, Peter Maydell, 2020/05/11
- [PULL 33/34] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA, Peter Maydell, 2020/05/11
- [PULL 34/34] target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed), Peter Maydell, 2020/05/11
- [PULL 31/34] target/arm: Restrict TCG cpus to TCG accel, Peter Maydell, 2020/05/11