[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH-for-5.1 v2 24/54] hw/riscv/sifive_u: Rename MachineClass::init()
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH-for-5.1 v2 24/54] hw/riscv/sifive_u: Rename MachineClass::init() |
Date: |
Mon, 6 Apr 2020 19:47:13 +0200 |
As there already is the riscv_sifive_u_soc_init() method,
rename riscv_sifive_u_init() as riscv_sifive_u_machine_init().
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
hw/riscv/sifive_u.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7bf1f30a35..e13ab34de4 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -312,7 +312,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
g_free(nodename);
}
-static void riscv_sifive_u_init(MachineState *machine)
+static void riscv_sifive_u_machine_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_u_memmap;
SiFiveUState *s = RISCV_U_MACHINE(machine);
@@ -606,7 +606,7 @@ static void riscv_sifive_u_machine_class_init(ObjectClass
*oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "RISC-V Board compatible with SiFive U SDK";
- mc->init = riscv_sifive_u_init;
+ mc->init = riscv_sifive_u_machine_init;
mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
mc->default_cpus = mc->min_cpus;
--
2.21.1
- [PATCH-for-5.1 v2 18/54] hw/pci-host/pnv_phb3: Move some code from realize() to init(), (continued)
- [PATCH-for-5.1 v2 18/54] hw/pci-host/pnv_phb3: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 19/54] hw/riscv/sifive_e: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 20/54] hw/riscv/sifive_u: Use single type_init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 16/54] hw/arm/xlnx-zynqmp: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 17/54] hw/microblaze/xlnx-zynqmp-pmu: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 12/54] hw/arm/stm32f205_soc: Store MemoryRegion in STM32F205State, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 21/54] hw/riscv/sifive_u: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 22/54] hw/riscv/sifive_u: Store MemoryRegion in SiFiveUSoCState, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 25/54] scripts/coccinelle: Catch missing error_propagate() calls in realize(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 23/54] hw/riscv/sifive_u: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 24/54] hw/riscv/sifive_u: Rename MachineClass::init(),
Philippe Mathieu-Daudé <=
- [PATCH-for-5.1 v2 27/54] hw/arm/stm32f*05_soc: Add missing error-propagation code, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 28/54] hw/arm/aspeed: Add missing error-propagation code, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 26/54] hw/arm/fsl-imx: Add missing error-propagation code, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 29/54] hw/arm/allwinner-a10: Add missing error-propagation code, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 30/54] hw/arm/msf2-soc: Add missing error-propagation code, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 32/54] hw/arm/armv7m: Add missing error-propagation code, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 34/54] hw/microblaze/xlnx-zynqmp-pmu: Add missing error-propagation code, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 36/54] hw/block/onenand: Add missing error-propagation code, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 33/54] hw/intc/arm_gicv3_its_kvm: Add missing error-propagation code, Philippe Mathieu-Daudé, 2020/04/06