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[PATCH-for-5.1 v2 20/54] hw/riscv/sifive_u: Use single type_init()
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH-for-5.1 v2 20/54] hw/riscv/sifive_u: Use single type_init() |
Date: |
Mon, 6 Apr 2020 19:47:09 +0200 |
We can use a single type_init() to call multiple type_register*().
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
hw/riscv/sifive_u.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 998666c91f..9c90c94c33 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -601,13 +601,6 @@ static const TypeInfo riscv_sifive_u_soc_type_info = {
.class_init = riscv_sifive_u_soc_class_init,
};
-static void riscv_sifive_u_soc_register_types(void)
-{
- type_register_static(&riscv_sifive_u_soc_type_info);
-}
-
-type_init(riscv_sifive_u_soc_register_types)
-
static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -627,9 +620,10 @@ static const TypeInfo riscv_sifive_u_machine_typeinfo = {
.instance_size = sizeof(SiFiveUState),
};
-static void riscv_sifive_u_machine_init_register_types(void)
+static void riscv_sifive_u_register_types(void)
{
+ type_register_static(&riscv_sifive_u_soc_type_info);
type_register_static(&riscv_sifive_u_machine_typeinfo);
}
-type_init(riscv_sifive_u_machine_init_register_types)
+type_init(riscv_sifive_u_register_types)
--
2.21.1
- [PATCH-for-5.1 v2 08/54] hw/arm/fsl-imx6: Simplify checks on 'smp_cpus' count, (continued)
- [PATCH-for-5.1 v2 08/54] hw/arm/fsl-imx6: Simplify checks on 'smp_cpus' count, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 10/54] hw/arm/fsl-imx31: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 13/54] hw/arm/stm32f205_soc: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 11/54] hw/arm/msf2-soc: Store MemoryRegion in MSF2State, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 06/54] hw/arm/aspeed_soc: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 15/54] hw/arm/xlnx-zynqmp: Split xlnx_zynqmp_create_rpu() as init + realize, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 14/54] hw/arm/xlnx-zynqmp: Use single propagate_error() call, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 18/54] hw/pci-host/pnv_phb3: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 19/54] hw/riscv/sifive_e: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 20/54] hw/riscv/sifive_u: Use single type_init(),
Philippe Mathieu-Daudé <=
- [PATCH-for-5.1 v2 16/54] hw/arm/xlnx-zynqmp: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 17/54] hw/microblaze/xlnx-zynqmp-pmu: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 12/54] hw/arm/stm32f205_soc: Store MemoryRegion in STM32F205State, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 21/54] hw/riscv/sifive_u: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 22/54] hw/riscv/sifive_u: Store MemoryRegion in SiFiveUSoCState, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 25/54] scripts/coccinelle: Catch missing error_propagate() calls in realize(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 23/54] hw/riscv/sifive_u: Move some code from realize() to init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 24/54] hw/riscv/sifive_u: Rename MachineClass::init(), Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 27/54] hw/arm/stm32f*05_soc: Add missing error-propagation code, Philippe Mathieu-Daudé, 2020/04/06
- [PATCH-for-5.1 v2 28/54] hw/arm/aspeed: Add missing error-propagation code, Philippe Mathieu-Daudé, 2020/04/06