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Re: [PATCH v5 13/60] target/riscv: vector single-width bit shift instruc
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v5 13/60] target/riscv: vector single-width bit shift instructions |
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Date: |
Fri, 13 Mar 2020 23:07:59 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, GVSUF)
> \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
> \
> +{
> \
> + if (!opivx_check(s, a)) {
> \
> + return false;
> \
> + }
> \
> +
> \
> + if (a->vm && s->vl_eq_vlmax) {
> \
> + TCGv_i32 src1 = tcg_temp_new_i32();
> \
> + TCGv tmp = tcg_temp_new();
> \
> + gen_get_gpr(tmp, a->rs1);
> \
> + tcg_gen_trunc_tl_i32(src1, tmp);
> \
> + tcg_gen_gvec_##GVSUF(8 << s->sew, vreg_ofs(s, a->rd),
> \
> + vreg_ofs(s, a->rs2), src1, MAXSZ(s), MAXSZ(s));
> \
Incorrect first argument.
Prefer an inline funtion helper.
Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
r~
- [PATCH v5 10/60] target/riscv: vector widening integer add and subtract, (continued)
- [PATCH v5 12/60] target/riscv: vector bitwise logical instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 13/60] target/riscv: vector single-width bit shift instructions, LIU Zhiwei, 2020/03/12
- Re: [PATCH v5 13/60] target/riscv: vector single-width bit shift instructions,
Richard Henderson <=
- [PATCH v5 14/60] target/riscv: vector narrowing integer right shift instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 15/60] target/riscv: vector integer comparison instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 16/60] target/riscv: vector integer min/max instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 18/60] target/riscv: vector integer divide instructions, LIU Zhiwei, 2020/03/12