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[PULL 10/52] target/arm: Use bit 55 explicitly for pauth
From: |
Peter Maydell |
Subject: |
[PULL 10/52] target/arm: Use bit 55 explicitly for pauth |
Date: |
Fri, 21 Feb 2020 13:06:58 +0000 |
From: Richard Henderson <address@hidden>
The psuedocode in aarch64/functions/pac/auth/Auth and
aarch64/functions/pac/strip/Strip always uses bit 55 for
extfield and do not consider if the current regime has 2 ranges.
Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/pauth_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
index 9746e32bf81..b909630317e 100644
--- a/target/arm/pauth_helper.c
+++ b/target/arm/pauth_helper.c
@@ -320,7 +320,8 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t
ptr, uint64_t modifier,
static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
{
- uint64_t extfield = -param.select;
+ /* Note that bit 55 is used whether or not the regime has 2 ranges. */
+ uint64_t extfield = sextract64(ptr, 55, 1);
int bot_pac_bit = 64 - param.tsz;
int top_pac_bit = 64 - 8 * param.tbi;
--
2.20.1
- [PULL 00/52] target-arm queue, Peter Maydell, 2020/02/21
- [PULL 01/52] aspeed/scu: Create separate write callbacks, Peter Maydell, 2020/02/21
- [PULL 02/52] aspeed/scu: Implement chip ID register, Peter Maydell, 2020/02/21
- [PULL 03/52] hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register, Peter Maydell, 2020/02/21
- [PULL 04/52] mainstone: Make providing flash images non-mandatory, Peter Maydell, 2020/02/21
- [PULL 05/52] z2: Make providing flash images non-mandatory, Peter Maydell, 2020/02/21
- [PULL 06/52] target/arm: Flush high bits of sve register after AdvSIMD EXT, Peter Maydell, 2020/02/21
- [PULL 07/52] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX, Peter Maydell, 2020/02/21
- [PULL 10/52] target/arm: Use bit 55 explicitly for pauth,
Peter Maydell <=
- [PULL 11/52] target/arm: Fix select for aa64_va_parameters_both, Peter Maydell, 2020/02/21
- [PULL 08/52] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN, Peter Maydell, 2020/02/21
- [PULL 09/52] target/arm: Flush high bits of sve register after AdvSIMD INS, Peter Maydell, 2020/02/21
- [PULL 12/52] target/arm: Remove ttbr1_valid check from get_phys_addr_lpae, Peter Maydell, 2020/02/21
- [PULL 15/52] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan, Peter Maydell, 2020/02/21
- [PULL 13/52] target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid, Peter Maydell, 2020/02/21
- [PULL 14/52] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers, Peter Maydell, 2020/02/21
- [PULL 17/52] target/arm: Define and use any_predinv isar_feature test, Peter Maydell, 2020/02/21
- [PULL 16/52] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions, Peter Maydell, 2020/02/21
- [PULL 20/52] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field, Peter Maydell, 2020/02/21