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[PATCH v5 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits
From: |
Richard Henderson |
Subject: |
[PATCH v5 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits |
Date: |
Wed, 29 Jan 2020 15:55:49 -0800 |
We are about to expand the number of mmuidx to 10, and so need 4 bits.
For the benefit of reading the number out of -d exec, align it to the
penultimate nibble.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 11f54556c9..893b1f1918 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3207,7 +3207,7 @@ typedef ARMCPU ArchCPU;
* We put flags which are shared between 32 and 64 bit mode at the top
* of the word, and flags which apply to only one mode at the bottom.
*
- * 31 21 18 14 9 0
+ * 31 20 18 14 9 0
* +--------------+-----+-----+----------+--------------+
* | | | TBFLAG_A32 | |
* | | +-----+----------+ TBFLAG_AM32 |
@@ -3215,19 +3215,19 @@ typedef ARMCPU ArchCPU;
* | | +-------------------------|
* | | | TBFLAG_A64 |
* +--------------+-----------+-------------------------+
- * 31 21 14 0
+ * 31 20 14 0
*
* Unless otherwise noted, these bits are cached in env->hflags.
*/
FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
-FIELD(TBFLAG_ANY, MMUIDX, 28, 3)
-FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1)
-FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */
+FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
+FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */
+FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
+FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
/* Target EL if we take a floating-point-disabled exception */
-FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)
-FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
+FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
/* For A-profile only, target EL for debug exceptions. */
-FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2)
+FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
/*
* Bit usage when in AArch32 state, both A- and M-profile.
--
2.20.1
- [PATCH v5 05/41] target/arm: Update CNTVCT_EL0 for VHE, (continued)
- [PATCH v5 05/41] target/arm: Update CNTVCT_EL0 for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 04/41] target/arm: Add TTBR1_EL2, Richard Henderson, 2020/01/29
- [PATCH v5 06/41] target/arm: Split out vae1_tlbmask, Richard Henderson, 2020/01/29
- [PATCH v5 07/41] target/arm: Split out alle1_tlbmask, Richard Henderson, 2020/01/29
- [PATCH v5 08/41] target/arm: Simplify tlb_force_broadcast alternatives, Richard Henderson, 2020/01/29
- [PATCH v5 09/41] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*, Richard Henderson, 2020/01/29
- [PATCH v5 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*, Richard Henderson, 2020/01/29
- [PATCH v5 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2, Richard Henderson, 2020/01/29
- [PATCH v5 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01], Richard Henderson, 2020/01/29
- [PATCH v5 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3, Richard Henderson, 2020/01/29
- [PATCH v5 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits,
Richard Henderson <=
- [PATCH v5 15/41] target/arm: Recover 4 bits from TBFLAGs, Richard Henderson, 2020/01/29
- [PATCH v5 17/41] target/arm: Rearrange ARMMMUIdxBit, Richard Henderson, 2020/01/29
- [PATCH v5 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, Richard Henderson, 2020/01/29
- [PATCH v5 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions, Richard Henderson, 2020/01/29
- [PATCH v5 19/41] target/arm: Reorganize ARMMMUIdx, Richard Henderson, 2020/01/29
- [PATCH v5 20/41] target/arm: Add regime_has_2_ranges, Richard Henderson, 2020/01/29
- [PATCH v5 23/41] target/arm: Update aa64_zva_access for EL2, Richard Henderson, 2020/01/29
- [PATCH v5 21/41] target/arm: Update arm_mmu_idx for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 22/41] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 25/41] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2020/01/29