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[PATCH v1 14/36] target/riscv: Add Hypervisor virtual CSRs accesses
|
From: |
Alistair Francis |
|
Subject: |
[PATCH v1 14/36] target/riscv: Add Hypervisor virtual CSRs accesses |
|
Date: |
Mon, 9 Dec 2019 10:11:17 -0800 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/csr.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index aaca1a6a0f..74e911af08 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -985,6 +985,30 @@ static int write_vsatp(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
+static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mtval2;
+ return 0;
+}
+
+static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->mtval2 = val;
+ return 0;
+}
+
+static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mtinst;
+ return 0;
+}
+
+static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->mtinst = val;
+ return 0;
+}
+
/* Physical Memory Protection */
static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -1208,6 +1232,9 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VSTVAL] = { hmode, read_vstval, write_vstval
},
[CSR_VSATP] = { hmode, read_vsatp, write_vsatp
},
+ [CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2
},
+ [CSR_MTINST] = { hmode, read_mtinst, write_mtinst
},
+
/* Physical Memory Protection */
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
--
2.24.0
- [PATCH v1 04/36] target/riscv: Add the Hypervisor CSRs to CPUState, (continued)
- [PATCH v1 04/36] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/12/09
- [PATCH v1 05/36] target/riscv: Add support for the new execption numbers, Alistair Francis, 2019/12/09
- [PATCH v1 06/36] target/riscv: Rename the H irqs to VS irqs, Alistair Francis, 2019/12/09
- [PATCH v1 07/36] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/12/09
- [PATCH v1 08/36] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/12/09
- [PATCH v1 09/36] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2019/12/09
- [PATCH v1 10/36] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/12/09
- [PATCH v1 11/36] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/12/09
- [PATCH v1 12/36] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/12/09
- [PATCH v1 13/36] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/12/09
- [PATCH v1 14/36] target/riscv: Add Hypervisor virtual CSRs accesses,
Alistair Francis <=
- [PATCH v1 15/36] target/riscv: Convert mstatus to pointers, Alistair Francis, 2019/12/09
- [PATCH v1 16/36] target/riscv: Add virtual register swapping function, Alistair Francis, 2019/12/09
- [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension, Alistair Francis, 2019/12/09
- [PATCH v1 18/36] target/riscv: Extend the MIE CSR to support virtulisation, Alistair Francis, 2019/12/09
- [PATCH v1 19/36] target/riscv: Extend the SIP CSR to support virtulisation, Alistair Francis, 2019/12/09
- [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/12/09
- [PATCH v1 21/36] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/12/09
- [PATCH v1 22/36] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/12/09
- [PATCH v1 23/36] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/12/09
- [PATCH v1 24/36] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/12/09