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[PATCH v1 09/36] target/riscv: Fix CSR perm checking for HS mode
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From: |
Alistair Francis |
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Subject: |
[PATCH v1 09/36] target/riscv: Fix CSR perm checking for HS mode |
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Date: |
Mon, 9 Dec 2019 10:11:04 -0800 |
Update the CSR permission checking to work correctly when we are in
HS-mode.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/csr.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6a0a59edfd..eebfc1823d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -802,12 +802,22 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
/* check privileges and return -1 if check fails */
#if !defined(CONFIG_USER_ONLY)
- int csr_priv = get_field(csrno, 0x300);
+ int effective_priv = env->priv;
int read_only = get_field(csrno, 0xC00) == 3;
- if ((!env->debugger) && (env->priv < csr_priv)) {
- return -1;
+
+ if (riscv_has_ext(env, RVH) &&
+ env->priv == PRV_S &&
+ !riscv_cpu_virt_enabled(env)) {
+ /*
+ * We are in S mode without virtualisation, therefore we are in HS
Mode.
+ * Add 1 to the effective privledge level to allow us to access the
+ * Hypervisor CSRs.
+ */
+ effective_priv++;
}
- if (write_mask && read_only) {
+
+ if ((write_mask && read_only) ||
+ (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
return -1;
}
#endif
--
2.24.0
- [PATCH v1 00/36] Add RISC-V Hypervisor Extension v0.5, Alistair Francis, 2019/12/09
- [PATCH v1 01/36] target/riscv: Convert MIP CSR to target_ulong, Alistair Francis, 2019/12/09
- [PATCH v1 02/36] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/12/09
- [PATCH v1 03/36] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/12/09
- [PATCH v1 04/36] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/12/09
- [PATCH v1 05/36] target/riscv: Add support for the new execption numbers, Alistair Francis, 2019/12/09
- [PATCH v1 06/36] target/riscv: Rename the H irqs to VS irqs, Alistair Francis, 2019/12/09
- [PATCH v1 07/36] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/12/09
- [PATCH v1 08/36] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/12/09
- [PATCH v1 09/36] target/riscv: Fix CSR perm checking for HS mode,
Alistair Francis <=
- [PATCH v1 10/36] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/12/09
- [PATCH v1 11/36] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/12/09
- [PATCH v1 12/36] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/12/09
- [PATCH v1 13/36] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/12/09
- [PATCH v1 14/36] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/12/09
- [PATCH v1 15/36] target/riscv: Convert mstatus to pointers, Alistair Francis, 2019/12/09
- [PATCH v1 16/36] target/riscv: Add virtual register swapping function, Alistair Francis, 2019/12/09
- [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension, Alistair Francis, 2019/12/09
- [PATCH v1 18/36] target/riscv: Extend the MIE CSR to support virtulisation, Alistair Francis, 2019/12/09
- [PATCH v1 19/36] target/riscv: Extend the SIP CSR to support virtulisation, Alistair Francis, 2019/12/09