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Re: [PATCH v36 11/17] target/avr: Add limited support for USART and 16 b
From: |
Aleksandar Markovic |
Subject: |
Re: [PATCH v36 11/17] target/avr: Add limited support for USART and 16 bit timer peripherals |
Date: |
Wed, 27 Nov 2019 21:02:00 +0100 |
On Wed, Nov 27, 2019 at 7:43 PM Aleksandar Markovic
<address@hidden> wrote:
>
> > > +/* Offsets of registers. */
> > > +#define USART_DR 0x06
> > > +#define USART_CSRA 0x00
> > > +#define USART_CSRB 0x01
> > > +#define USART_CSRC 0x02
> > > +#define USART_BRRH 0x05
> > > +#define USART_BRRL 0x04
> > > +
> > > +/* Relevant bits in regiters. */
> > > +#define USART_CSRA_RXC (1 << 7)
> > > +#define USART_CSRA_TXC (1 << 6)
> > > +#define USART_CSRA_DRE (1 << 5)
> > > +#define USART_CSRA_MPCM (1 << 0)
> > > +
> > > +#define USART_CSRB_RXCIE (1 << 7)
> > > +#define USART_CSRB_TXCIE (1 << 6)
> > > +#define USART_CSRB_DREIE (1 << 5)
> > > +#define USART_CSRB_RXEN (1 << 4)
> > > +#define USART_CSRB_TXEN (1 << 3)
> > > +#define USART_CSRB_CSZ2 (1 << 2)
> > > +#define USART_CSRB_RXB8 (1 << 1)
> > > +#define USART_CSRB_TXB8 (1 << 0)
> > > +
> > > +#define USART_CSRC_MSEL1 (1 << 7)
> > > +#define USART_CSRC_MSEL0 (1 << 6)
> > > +#define USART_CSRC_PM1 (1 << 5)
> > > +#define USART_CSRC_PM0 (1 << 4)
> > > +#define USART_CSRC_CSZ1 (1 << 2)
> > > +#define USART_CSRC_CSZ0 (1 << 1)
> >
> > The previous definitions can go into hw/char/avr_usart.c.
> >
>
> Why?
Seriously, Philippe, why move this from their perfect cosy place in the header?
If the answer is "because most of others in QEMU do", I don't know...
I wouldn't consider that a legitimate reason - at least not in this
particular case.
Aleksandar
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