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[Qemu-devel] [PATCH 38/67] target/arm: Convert Table Branch
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 38/67] target/arm: Convert Table Branch |
Date: |
Fri, 26 Jul 2019 10:50:03 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 62 +++++++++++++++++++++++-------------------
target/arm/t32.decode | 8 +++++-
2 files changed, 41 insertions(+), 29 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 87cbadc6cb..9c6623fb6b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9979,6 +9979,37 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
return true;
}
+static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half)
+{
+ TCGv_i32 addr, tmp;
+
+ tmp = load_reg(s, a->rm);
+ if (half) {
+ tcg_gen_add_i32(tmp, tmp, tmp);
+ }
+ addr = load_reg(s, a->rn);
+ tcg_gen_add_i32(addr, addr, tmp);
+
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
+ half ? MO_UW | s->be_data : MO_UB);
+ tcg_temp_free_i32(addr);
+
+ tcg_gen_add_i32(tmp, tmp, tmp);
+ tcg_gen_addi_i32(tmp, tmp, s->pc_read);
+ store_reg(s, 15, tmp);
+ return true;
+}
+
+static bool trans_TBB(DisasContext *s, arg_tbranch *a)
+{
+ return op_tbranch(s, a, false);
+}
+
+static bool trans_TBH(DisasContext *s, arg_tbranch *a)
+{
+ return op_tbranch(s, a, true);
+}
+
/*
* Supervisor call
*/
@@ -10358,9 +10389,7 @@ static bool thumb_insn_is_16bit(DisasContext *s,
uint32_t insn)
/* Translate a 32-bit thumb instruction. */
static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
{
- uint32_t rd, rn, rm, rs;
- TCGv_i32 tmp;
- TCGv_i32 addr;
+ uint32_t rd, rn, rs;
int op;
/*
@@ -10406,7 +10435,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
rn = (insn >> 16) & 0xf;
rs = (insn >> 12) & 0xf;
rd = (insn >> 8) & 0xf;
- rm = insn & 0xf;
switch ((insn >> 25) & 0xf) {
case 0: case 1: case 2: case 3:
/* 16-bit instructions. Should never happen. */
@@ -10479,30 +10507,8 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
/* Load/store exclusive, in decodetree */
goto illegal_op;
} else if ((insn & (7 << 5)) == 0) {
- /* Table Branch. */
- if (rn == 15) {
- addr = tcg_temp_new_i32();
- tcg_gen_movi_i32(addr, s->pc_read);
- } else {
- addr = load_reg(s, rn);
- }
- tmp = load_reg(s, rm);
- tcg_gen_add_i32(addr, addr, tmp);
- if (insn & (1 << 4)) {
- /* tbh */
- tcg_gen_add_i32(addr, addr, tmp);
- tcg_temp_free_i32(tmp);
- tmp = tcg_temp_new_i32();
- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
- } else { /* tbb */
- tcg_temp_free_i32(tmp);
- tmp = tcg_temp_new_i32();
- gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
- }
- tcg_temp_free_i32(addr);
- tcg_gen_shli_i32(tmp, tmp, 1);
- tcg_gen_addi_i32(tmp, tmp, s->pc_read);
- store_reg(s, 15, tmp);
+ /* Table Branch, in decodetree */
+ goto illegal_op;
} else {
/* Load/store exclusive, load-acq/store-rel, in decodetree */
goto illegal_op;
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index f8d8660466..17e6dae688 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -487,7 +487,7 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........
@ldstd_ri8 w=0 p=1
STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1
LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1
-# Load/Store Exclusive and Load-Acquire/Store-Release
+# Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch
@strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \
&strex rt2=15 imm=%imm8x4
@@ -531,6 +531,12 @@ LDA 1110 1000 1101 .... .... 1111 1010 1111
@ldrex_0
LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0
LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0
+&tbranch rn rm
+@tbranch .... .... .... rn:4 .... .... .... rm:4 &tbranch
+
+TBB 1110 1000 1101 .... 1111 0000 0000 .... @tbranch
+TBH 1110 1000 1101 .... 1111 0000 0001 .... @tbranch
+
# Parallel addition and subtraction
SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm
--
2.17.1
- [Qemu-devel] [PATCH 26/67] target/arm: Convert Packing, unpacking, saturation, and reversal, (continued)
- [Qemu-devel] [PATCH 26/67] target/arm: Convert Packing, unpacking, saturation, and reversal, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 22/67] target/arm: Convert load/store (register, immediate, literal), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 28/67] target/arm: Convert MOVW, MOVT, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 30/67] target/arm: Convert B, BL, BLX (immediate), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 29/67] target/arm: Convert LDM, STM, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 32/67] target/arm: Convert RFE and SRS, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 35/67] target/arm: Convert SETEND, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 31/67] target/arm: Convert SVC, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 38/67] target/arm: Convert Table Branch,
Richard Henderson <=
- [Qemu-devel] [PATCH 39/67] target/arm: Convert SG, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 34/67] target/arm: Convert CPS (privileged), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 40/67] target/arm: Convert TT, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 42/67] target/arm: Simplify disas_arm_insn, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 37/67] target/arm: Convert Unallocated memory hint, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 44/67] target/arm: Convert T16 data-processing (two low regs), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 45/67] target/arm: Convert T16 load/store (register offset), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 36/67] target/arm: Convert PLI, PLD, PLDW, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 47/67] target/arm: Convert T16 add pc/sp (immediate), Richard Henderson, 2019/07/26