[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree |
Date: |
Fri, 26 Jul 2019 10:50:08 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 6 ++++++
target/arm/Makefile.objs | 6 ++++++
target/arm/t16.decode | 20 ++++++++++++++++++++
3 files changed, 32 insertions(+)
create mode 100644 target/arm/t16.decode
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 65a74a963b..db93b12608 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7608,6 +7608,7 @@ static int t32_branch24(DisasContext *s, int x)
#include "decode-a32.inc.c"
#include "decode-a32-uncond.inc.c"
#include "decode-t32.inc.c"
+#include "decode-t16.inc.c"
#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
# pragma GCC diagnostic pop
@@ -10559,6 +10560,11 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
TCGv_i32 tmp2;
TCGv_i32 addr;
+ if (disas_t16(s, insn)) {
+ return;
+ }
+ /* fall back to legacy decoder */
+
switch (insn >> 12) {
case 0: case 1:
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index 7806b4dac0..cf26c16f5f 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -43,12 +43,18 @@ target/arm/decode-t32.inc.c:
$(SRC_PATH)/target/arm/t32.decode $(DECODETREE)
$(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
+target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
+ $(call quiet-command,\
+ $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\
+ "GEN", $(TARGET_DIR)$@)
+
target/arm/translate-sve.o: target/arm/decode-sve.inc.c
target/arm/translate.o: target/arm/decode-vfp.inc.c
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
target/arm/translate.o: target/arm/decode-a32.inc.c
target/arm/translate.o: target/arm/decode-a32-uncond.inc.c
target/arm/translate.o: target/arm/decode-t32.inc.c
+target/arm/translate.o: target/arm/decode-t16.inc.c
obj-y += tlb_helper.o debug_helper.o
obj-y += translate.o op_helper.o
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
new file mode 100644
index 0000000000..e954f61fe4
--- /dev/null
+++ b/target/arm/t16.decode
@@ -0,0 +1,20 @@
+# Thumb1 instructions
+#
+# Copyright (c) 2019 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
--
2.17.1
- [Qemu-devel] [PATCH 31/67] target/arm: Convert SVC, (continued)
- [Qemu-devel] [PATCH 31/67] target/arm: Convert SVC, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 38/67] target/arm: Convert Table Branch, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 39/67] target/arm: Convert SG, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 34/67] target/arm: Convert CPS (privileged), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 40/67] target/arm: Convert TT, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 42/67] target/arm: Simplify disas_arm_insn, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 37/67] target/arm: Convert Unallocated memory hint, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 44/67] target/arm: Convert T16 data-processing (two low regs), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 45/67] target/arm: Convert T16 load/store (register offset), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree,
Richard Henderson <=
- [Qemu-devel] [PATCH 36/67] target/arm: Convert PLI, PLD, PLDW, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 47/67] target/arm: Convert T16 add pc/sp (immediate), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 46/67] target/arm: Convert T16 load/store (immediate offset), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 48/67] target/arm: Convert T16 load/store multiple, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 49/67] target/arm: Convert T16 add/sub (3 low, 2 low and imm), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 50/67] target/arm: Convert T16 one low register and immediate, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 51/67] target/arm: Convert T16 branch and exchange, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 41/67] target/arm: Simplify disas_thumb2_insn, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 53/67] target/arm: Convert T16 adjust sp (immediate), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 55/67] target/arm: Convert T16, Change processor state, Richard Henderson, 2019/07/26