Re: [Qemu-devel] [PATCH for 4.2] target/arm: generate a custom MIDR for -cpu max

[Laurent Desnogues]

On Fri, Jul 26, 2019 at 9:24 AM Alex Bennée <address@hidden> wrote:
>
>
> Peter Maydell <address@hidden> writes:
>
> > On Tue, 23 Jul 2019 at 12:33, Alex Bennée <address@hidden> wrote:
[...]
> >  /*
> >   * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
> >   * one and try to apply errata workarounds or use impdef features we
> >   * don't provide.
> >   * An IMPLEMENTER field of 0 means "reserved for software use";
> >   * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
> >   * to see which features are present";
> >   * the VARIANT, PARTNUM and REVISION fields are all implementation
> >   * defined and we choose to leave them all at zero.
> >   */
> >
> > It's also a bit inconsistent to do an explicit deposit of 0
> > for the IMPLEMENTER field but not for the VARIANT/PARTNUM/REVISION.
> >
> > I wonder if we should put 0x51 (ascii 'Q') in the PARTNUM field;
> > then if somebody really needs to distinguish QEMU from random
> > other software-models they have a way to do it.
>
> Q is reserved for Qualcomm - It would be nice if ARM could assign QEMU a
> code but I suspect that's not part of the business model.

That was my reaction at first too, but that Q is reserved for the
Implementer field, while Peter is proposing to put it in the PartNum
field :-)

Laurent