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Re: [Qemu-devel] pl031 time across vm save/reload

From: Paolo Bonzini
Subject: Re: [Qemu-devel] pl031 time across vm save/reload
Date: Fri, 5 Jul 2019 12:32:20 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2

On 05/07/19 12:21, Peter Maydell wrote:
> On Fri, 5 Jul 2019 at 11:13, Paolo Bonzini <address@hidden> wrote:
>> On 05/07/19 11:58, Peter Maydell wrote:
>>> On Fri, 5 Jul 2019 at 10:48, Paolo Bonzini <address@hidden> wrote:
>>>> You're right, the compatibility causes wrong behavior for the default
>>>> -rtc settings (the RC pauses across migration).  The right thing to do
>>>> would be to store the base rather than the offset: that is, you store
>>>> the time at which LR was written.  Then the offset is s->lr - s->base
>>>> and it's independent of the machine on which the rtc_clock is being read.
>>> Right. How do we handle this for back-compat purposes? I guess
>>> we need to have a new migration subsection, so if it's present
>>> it has the 'base' value and we ignore the 'offset' in the
>>> main migration data, and if it's not present we assume an
>>> old->new migration and use the existing offset code. New->old
>>> migration would not be possible as the new subsection is
>>> always-present.
>> Yes, something like that but I would just bump the version.  Version 1
>> has the old meaning for the first field, version 2 has the new meaning.
> Yeah, we could do that. I thought we preferred to avoid using
> version-numbers for migration though these days ? (cc'ing DG
> in case he has an opinion.)

Yeah I suppose a subsection would make it easier to keep the old broken
behavior for old machine types.  It would be a bit more code.

>> And also, since our brains are fresh on pl031... currently s->lr is
>> always 0; besides the bug that writing RTC_LR should update it, the
>> datasheet says the counter counts up from 1 so perhaps at startup s->lr
>> should be set to a nonzero value?   That would be
>> qemu_ref_timedate(QEMU_CLOCK_VIRTUAL) - 1.
> The 'summary of RTC registers' section in the datasheet says
> that RTCLR's reset value is zero...

Right, but RTCDR doesn't return the current wallclock after power up on
real hardware, doesn't it?  So the choices are 1) RTCLR returns 0 and it
looks like the board was powered on in the seventies; 2) RTCLR is not 0
and it looks like some firmware ran initialized RTCLR.


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