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[Qemu-devel] [PULL 40/49] target/ppc: decode target register in VSX_EXTR
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 40/49] target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time |
Date: |
Tue, 2 Jul 2019 16:08:48 +1000 |
From: Mark Cave-Ayland <address@hidden>
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/helper.h | 4 ++--
target/ppc/int_helper.c | 12 ++++--------
target/ppc/translate/vsx-impl.inc.c | 10 +++++-----
3 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 7ed9effff2..3d5150a524 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -534,8 +534,8 @@ DEF_HELPER_3(xvrspip, void, env, vsr, vsr)
DEF_HELPER_3(xvrspiz, void, env, vsr, vsr)
DEF_HELPER_4(xxperm, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xxpermr, void, env, vsr, vsr, vsr)
-DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
-DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
+DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32)
+DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32)
DEF_HELPER_3(xvxsigsp, void, env, vsr, vsr)
DEF_HELPER_2(efscfsi, i32, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 3b8939edcc..5c07ef3e4d 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1899,11 +1899,9 @@ VEXTRACT(uw, u32)
VEXTRACT(d, u64)
#undef VEXTRACT
-void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
- target_ulong xbn, uint32_t index)
+void helper_xxextractuw(CPUPPCState *env, ppc_vsr_t *xt,
+ ppc_vsr_t *xb, uint32_t index)
{
- ppc_vsr_t *xt = &env->vsr[xtn];
- ppc_vsr_t *xb = &env->vsr[xbn];
ppc_vsr_t t = { };
size_t es = sizeof(uint32_t);
uint32_t ext_index;
@@ -1917,11 +1915,9 @@ void helper_xxextractuw(CPUPPCState *env, target_ulong
xtn,
*xt = t;
}
-void helper_xxinsertw(CPUPPCState *env, target_ulong xtn,
- target_ulong xbn, uint32_t index)
+void helper_xxinsertw(CPUPPCState *env, ppc_vsr_t *xt,
+ ppc_vsr_t *xb, uint32_t index)
{
- ppc_vsr_t *xt = &env->vsr[xtn];
- ppc_vsr_t *xb = &env->vsr[xbn];
ppc_vsr_t t = *xt;
size_t es = sizeof(uint32_t);
int ins_index, i = 0;
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index e853ee1386..7a4b7cb8f9 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1632,7 +1632,7 @@ static void gen_xxsldwi(DisasContext *ctx)
#define VSX_EXTRACT_INSERT(name) \
static void gen_##name(DisasContext *ctx) \
{ \
- TCGv xt, xb; \
+ TCGv_ptr xt, xb; \
TCGv_i32 t0; \
TCGv_i64 t1; \
uint8_t uimm = UIMM4(ctx->opcode); \
@@ -1641,8 +1641,8 @@ static void gen_##name(DisasContext *ctx)
\
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- xt = tcg_const_tl(xT(ctx->opcode)); \
- xb = tcg_const_tl(xB(ctx->opcode)); \
+ xt = gen_vsr_ptr(xT(ctx->opcode)); \
+ xb = gen_vsr_ptr(xB(ctx->opcode)); \
t0 = tcg_temp_new_i32(); \
t1 = tcg_temp_new_i64(); \
/* \
@@ -1657,8 +1657,8 @@ static void gen_##name(DisasContext *ctx)
\
} \
tcg_gen_movi_i32(t0, uimm); \
gen_helper_##name(cpu_env, xt, xb, t0); \
- tcg_temp_free(xb); \
- tcg_temp_free(xt); \
+ tcg_temp_free_ptr(xb); \
+ tcg_temp_free_ptr(xt); \
tcg_temp_free_i32(t0); \
tcg_temp_free_i64(t1); \
}
--
2.21.0
- [Qemu-devel] [PULL 41/49] target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro, (continued)
- [Qemu-devel] [PULL 41/49] target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 44/49] spapr/xive: simplify spapr_irq_init_device() to remove the emulated init, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 37/49] target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.c, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 45/49] ppc/xive: Force the Physical CAM line value to group mode, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 35/49] target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 36/49] target/ppc: introduce GEN_VSX_HELPER_R3 macro to fpu_helper.c, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 33/49] target/ppc: introduce GEN_VSX_HELPER_X2 macro to fpu_helper.c, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 39/49] target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at translation time, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 32/49] target/ppc: introduce separate generator and helper for xscvqpdp, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 48/49] ppc/xive: Fix TM_PULL_POOL_CTX special operation, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 40/49] target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time,
David Gibson <=
- [Qemu-devel] [PULL 30/49] target/ppc: introduce separate VSX_CMP macro for xvcmp* instructions, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 46/49] ppc/xive: Make the PIPR register readonly, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 47/49] ppc/pnv: Rework cache watch model of PnvXIVE, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 49/49] spapr/xive: Add proper rollback to kvmppc_xive_connect(), David Gibson, 2019/07/02
- Re: [Qemu-devel] [PULL 00/49] ppc-for-4.1 queue 20190702, no-reply, 2019/07/02
- Re: [Qemu-devel] [PULL 00/49] ppc-for-4.1 queue 20190702, Peter Maydell, 2019/07/02