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[Qemu-devel] [PULL 46/49] ppc/xive: Make the PIPR register readonly
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 46/49] ppc/xive: Make the PIPR register readonly |
Date: |
Tue, 2 Jul 2019 16:08:54 +1000 |
From: Cédric Le Goater <address@hidden>
When the hypervisor (KVM) dispatches a vCPU on a HW thread, it restores
its thread interrupt context. The Pending Interrupt Priority Register
(PIPR) is computed from the Interrupt Pending Buffer (IPB) and stores
should not be allowed to change its value.
Fixes: 207d9fe98510 ("ppc/xive: introduce the XIVE interrupt thread context")
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/intc/xive.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 3b1f9520ae..534f56f86b 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -182,31 +182,31 @@ static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr
offset, unsigned size)
*/
static const uint8_t xive_tm_hw_view[] = {
- /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
- /* QW-1 OS */ 3, 3, 3, 3, 3, 3, 0, 3, 3, 3, 3, 3, 0, 0, 0, 0,
- /* QW-2 POOL */ 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
- /* QW-3 PHYS */ 3, 3, 3, 3, 0, 3, 0, 3, 3, 0, 0, 3, 3, 3, 3, 0,
+ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
+ 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */
+ 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
+ 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */
};
static const uint8_t xive_tm_hv_view[] = {
- /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
- /* QW-1 OS */ 3, 3, 3, 3, 3, 3, 0, 3, 3, 3, 3, 3, 0, 0, 0, 0,
- /* QW-2 POOL */ 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0,
- /* QW-3 PHYS */ 3, 3, 3, 3, 0, 3, 0, 3, 3, 0, 0, 3, 0, 0, 0, 0,
+ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
+ 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */
+ 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
+ 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */
};
static const uint8_t xive_tm_os_view[] = {
- /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
- /* QW-1 OS */ 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0,
- /* QW-2 POOL */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* QW-3 PHYS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
+ 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
};
static const uint8_t xive_tm_user_view[] = {
- /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* QW-1 OS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* QW-2 POOL */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* QW-3 PHYS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
};
/*
--
2.21.0
- [Qemu-devel] [PULL 37/49] target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.c, (continued)
- [Qemu-devel] [PULL 37/49] target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.c, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 45/49] ppc/xive: Force the Physical CAM line value to group mode, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 35/49] target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 36/49] target/ppc: introduce GEN_VSX_HELPER_R3 macro to fpu_helper.c, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 33/49] target/ppc: introduce GEN_VSX_HELPER_X2 macro to fpu_helper.c, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 39/49] target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at translation time, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 32/49] target/ppc: introduce separate generator and helper for xscvqpdp, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 48/49] ppc/xive: Fix TM_PULL_POOL_CTX special operation, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 40/49] target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 30/49] target/ppc: introduce separate VSX_CMP macro for xvcmp* instructions, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 46/49] ppc/xive: Make the PIPR register readonly,
David Gibson <=
- [Qemu-devel] [PULL 47/49] ppc/pnv: Rework cache watch model of PnvXIVE, David Gibson, 2019/07/02
- [Qemu-devel] [PULL 49/49] spapr/xive: Add proper rollback to kvmppc_xive_connect(), David Gibson, 2019/07/02
- Re: [Qemu-devel] [PULL 00/49] ppc-for-4.1 queue 20190702, no-reply, 2019/07/02
- Re: [Qemu-devel] [PULL 00/49] ppc-for-4.1 queue 20190702, Peter Maydell, 2019/07/02