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[Qemu-devel] [PATCH v2 3/4] disas/riscv: Fix `rdinstreth` constraint
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v2 3/4] disas/riscv: Fix `rdinstreth` constraint |
Date: |
Mon, 24 Jun 2019 16:42:35 -0700 |
From: Michael Clark <address@hidden>
The constraint for `rdinstreth` was comparing the csr number to 0xc80,
which is `cycleh` instead. Fix this.
Signed-off-by: Wladimir J. van der Laan <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
disas/riscv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 3ab4586f0a..bdcc70a68e 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -614,7 +614,7 @@ static const rvc_constraint rvcc_rdtime[] = {
rvc_rs1_eq_x0, rvc_csr_eq_0xc01, r
static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
rvc_csr_eq_0xc02, rvc_end };
static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
rvc_csr_eq_0xc80, rvc_end };
static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0,
rvc_csr_eq_0xc81, rvc_end };
-static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
rvc_csr_eq_0xc80, rvc_end };
+static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
rvc_csr_eq_0xc82, rvc_end };
static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003,
rvc_end };
static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002,
rvc_end };
static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0,
rvc_csr_eq_0x001, rvc_end };
@@ -1031,7 +1031,7 @@ const rv_opcode_data opcode_data[] = {
{ "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui,
rv_op_lui, rvcd_imm_nz },
{ "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli,
rv_op_srli, rv_op_srli, rvcd_imm_nz },
{ "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai,
rv_op_srai, rv_op_srai, rvcd_imm_nz },
- { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
rv_op_andi, rv_op_andi, rvcd_imm_nz },
+ { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
rv_op_andi, rv_op_andi },
{ "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub,
rv_op_sub },
{ "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor,
rv_op_xor },
{ "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or,
rv_op_or },
--
2.22.0
- [Qemu-devel] [PATCH v2 0/4] Miscellaneous patches from the RISC-V fork, Alistair Francis, 2019/06/24
- [Qemu-devel] [PATCH v2 1/4] target/riscv: Fix PMP range boundary address bug, Alistair Francis, 2019/06/24
- [Qemu-devel] [PATCH v2 3/4] disas/riscv: Fix `rdinstreth` constraint,
Alistair Francis <=
- [Qemu-devel] [PATCH v2 2/4] disas/riscv: Disassemble reserved compressed encodings as illegal, Alistair Francis, 2019/06/24
- [Qemu-devel] [PATCH v2 4/4] target/riscv: Implement riscv_cpu_unassigned_access, Alistair Francis, 2019/06/24
- Re: [Qemu-devel] [PATCH v2 0/4] Miscellaneous patches from the RISC-V fork, no-reply, 2019/06/24
- Re: [Qemu-devel] [PATCH v2 0/4] Miscellaneous patches from the RISC-V fork, Palmer Dabbelt, 2019/06/25