Re: [Qemu-devel] [PULL 01/48] target/arm: Vectorize USHL and SSHL

[Peter Maydell]

On Thu, 13 Jun 2019 at 13:14, Peter Maydell <address@hidden> wrote:
>
> From: Richard Henderson <address@hidden>
>
> These instructions shift left or right depending on the sign
> of the input, and 7 bits are significant to the shift.  This
> requires several masks and selects in addition to the actual
> shifts to form the complete answer.
>
> That said, the operation is still a small improvement even for
> two 64-bit elements -- 13 vector operations instead of 2 * 7
> integer operations.
>
> Signed-off-by: Richard Henderson <address@hidden>
> Message-id: address@hidden
> Reviewed-by: Peter Maydell <address@hidden>
> Signed-off-by: Peter Maydell <address@hidden>

Hi Richard -- I just noticed that this patch seems to
regress VSHL for AArch32.

     160:       f3026408        vshl.u8 d6, d8, d2
with
  d2: 429de8b85a8dee77
  d8: 279cd30880000000

now gives
  d6: 00000000008dee77
when previously both QEMU and real Cortex-A7 hardware
gave d6: all-zeroes.

(this is testcases/aarch32-all/insn_VSHL__INC.risu.bin
from Alex's set.)

I'm going to drop this patch from the pullreq.

thanks
-- PMM