[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 11/48] target/arm: Explicitly enable VFP short-vector
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/48] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max |
Date: |
Thu, 13 Jun 2019 13:13:56 +0100 |
At the moment our -cpu max for AArch32 supports VFP short-vectors
because we always implement them, even for CPUs which should
not have them. The following commits are going to switch to
using the correct ID-register-check to enable or disable short
vector support, so we need to turn it on explicitly for -cpu max,
because Cortex-A15 doesn't implement it.
We don't enable this for the AArch64 -cpu max, because the v8A
architecture never supports short-vectors.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/arm/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c8441fc07b7..2335659a852 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2023,6 +2023,10 @@ static void arm_max_initfn(Object *obj)
kvm_arm_set_cpu_features_from_host(cpu);
} else {
cortex_a15_initfn(obj);
+
+ /* old-style VFP short-vector support */
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+
#ifdef CONFIG_USER_ONLY
/* We don't set these in system emulation mode for the moment,
* since we don't correctly set (all of) the ID registers to
--
2.20.1
- [Qemu-devel] [PULL 00/48] target-arm queue, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 01/48] target/arm: Vectorize USHL and SSHL, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 02/48] target/arm: Use tcg_gen_gvec_bitsel, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 06/48] target/arm: Fix output of PAuth Auth, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 07/48] decodetree: Fix comparison of Field, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 12/48] target/arm: Convert the VSEL instructions to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 11/48] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max,
Peter Maydell <=
- [Qemu-devel] [PULL 08/48] target/arm: Add stubs for AArch32 VFP decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 10/48] target/arm: Fix Cortex-R5F MVFR values, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 20/48] target/arm: Convert VFP two-register transfer insns to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 05/48] hw/core/bus.c: Only the main system bus can have no parent, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 19/48] target/arm: Convert "single-precision" register moves to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 21/48] target/arm: Convert VFP VLDR and VSTR to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 04/48] hw/arm/smmuv3: Fix decoding of ID register range, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 03/48] target/arm: Implement NSACR gating of floating point, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 18/48] target/arm: Convert "double-precision" register moves to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 15/48] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree, Peter Maydell, 2019/06/13