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[Qemu-devel] [PATCH v1 17/23] s390x/tcg: Implement VECTOR FP PERFORM SIG
From: |
David Hildenbrand |
Subject: |
[Qemu-devel] [PATCH v1 17/23] s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION |
Date: |
Fri, 31 May 2019 12:44:26 +0200 |
The only FP instruction we can implement without an helper.
Signed-off-by: David Hildenbrand <address@hidden>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 42 +++++++++++++++++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index e86ade9e44..fa2e801747 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1240,6 +1240,8 @@
F(0xe78f, VFMA, VRR_e, V, 0, 0, 0, 0, vfma, 0, IF_VEC)
/* VECTOR FP MULTIPLY AND SUBTRACT */
F(0xe78e, VFMS, VRR_e, V, 0, 0, 0, 0, vfma, 0, IF_VEC)
+/* VECTOR FP PERFORM SIGN OPERATION */
+ F(0xe7cc, VFPSO, VRR_a, V, 0, 0, 0, 0, vfpso, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index b624c7a8aa..b80d2a7a88 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2727,3 +2727,45 @@ static DisasJumpType op_vfma(DisasContext *s, DisasOps
*o)
0, fn);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o)
+{
+ const uint8_t fpf = get_field(s->fields, m3);
+ const uint8_t m4 = get_field(s->fields, m4);
+ const uint8_t m5 = get_field(s->fields, m5);
+ const bool se = extract32(m4, 3, 1);
+ TCGv_i64 tmp;
+ int i;
+
+ if (fpf != FPF_LONG || extract32(m4, 0, 3) || m5 > 2) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ for (i = 0; i < 2; i++) {
+ read_vec_element_i64(tmp, get_field(s->fields, v2), i, ES_64);
+
+ switch (m5) {
+ case 0:
+ /* sign bit is inverted (complement) */
+ tcg_gen_xori_i64(tmp, tmp, 1ull << 63);
+ break;
+ case 1:
+ /* sign bit is set to one (negative) */
+ tcg_gen_ori_i64(tmp, tmp, 1ull << 63);
+ break;
+ case 2:
+ /* sign bit is set to zero (positive) */
+ tcg_gen_andi_i64(tmp, tmp, (1ull << 63) - 1);
+ break;
+ }
+
+ write_vec_element_i64(tmp, get_field(s->fields, v1), i, ES_64);
+ if (se) {
+ break;
+ }
+ }
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.20.1
- Re: [Qemu-devel] [PATCH v1 13/23] s390x/tcg: Implement VECTOR LOAD LENGTHENED, (continued)
[Qemu-devel] [PATCH v1 14/23] s390x/tcg: Implement VECTOR LOAD ROUNDED, David Hildenbrand, 2019/05/31
[Qemu-devel] [PATCH v1 15/23] s390x/tcg: Implement VECTOR FP MULTIPLY, David Hildenbrand, 2019/05/31
[Qemu-devel] [PATCH v1 16/23] s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT), David Hildenbrand, 2019/05/31
[Qemu-devel] [PATCH v1 17/23] s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION,
David Hildenbrand <=
[Qemu-devel] [PATCH v1 18/23] s390x/tcg: Implement VECTOR FP SQUARE ROOT, David Hildenbrand, 2019/05/31
[Qemu-devel] [PATCH v1 19/23] s390x/tcg: Implement VECTOR FP SUBTRACT, David Hildenbrand, 2019/05/31
[Qemu-devel] [PATCH v1 20/23] s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE, David Hildenbrand, 2019/05/31
[Qemu-devel] [PATCH v1 23/23] s390x: Bump the "qemu" CPU model up to a stripped-down z13, David Hildenbrand, 2019/05/31