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[Qemu-devel] [PULL 05/29] target/riscv: Use --static-decode for decodetr
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 05/29] target/riscv: Use --static-decode for decodetree |
Date: |
Sat, 25 May 2019 18:09:24 -0700 |
From: Richard Henderson <address@hidden>
The generated functions are only used within translate.c
and do not need to be global, or declared.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/Makefile.objs | 8 ++++----
target/riscv/translate.c | 3 ---
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 9c6c1093271e..c7a1b063edc2 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -7,14 +7,14 @@ decode32-$(TARGET_RISCV64) +=
$(SRC_PATH)/target/riscv/insn32-64.decode
target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
$(call quiet-command, \
- $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
- "GEN", $(TARGET_DIR)$@)
+ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
+ $(decode32-y), "GEN", $(TARGET_DIR)$@)
target/riscv/decode_insn16.inc.c: \
$(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
$(call quiet-command, \
- $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16
$<, \
- "GEN", $(TARGET_DIR)$@)
+ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
+ --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
target/riscv/decode_insn16.inc.c
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 928374242e83..b09158117f32 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -558,7 +558,6 @@ static int ex_rvc_register(DisasContext *ctx, int reg)
return 8 + reg;
}
-bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
@@ -701,8 +700,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
# endif
#endif
-bool decode_insn16(DisasContext *ctx, uint16_t insn);
-/* auto-generated decoder*/
#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
--
2.21.0
- [Qemu-devel] [PULL 14/29] riscv: virt: Allow specifying a CPU via commandline, (continued)
- [Qemu-devel] [PULL 14/29] riscv: virt: Allow specifying a CPU via commandline, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 15/29] target/riscv: Create settable CPU properties, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 06/29] target/riscv: Merge argument sets for insn32 and insn16, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 03/29] RISC-V: fix single stepping over ret and other branching instructions, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 13/29] linux-user/riscv: Add the CPU type as a comment, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 10/29] target/riscv: Split gen_arith_imm into functional and temp, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 09/29] target/riscv: Split RVC32 and RVC64 insns into separate files, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 05/29] target/riscv: Use --static-decode for decodetree,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 07/29] target/riscv: Merge argument decode for RVC shifti, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 02/29] target/riscv: Do not allow sfence.vma from user mode, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 01/29] SiFive RISC-V GPIO Device, Palmer Dabbelt, 2019/05/25
- Re: [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1, Peter Maydell, 2019/05/28