[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 02/29] target/riscv: Do not allow sfence.vma from use
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 02/29] target/riscv: Do not allow sfence.vma from user mode |
Date: |
Sat, 25 May 2019 18:09:21 -0700 |
From: Jonathan Behrens <address@hidden>
The 'sfence.vma' instruction is privileged, and should only ever be allowed
when executing in supervisor mode or higher.
Signed-off-by: Jonathan Behrens <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/op_helper.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index b7dc18a41e21..644d0fb35f16 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -145,9 +145,10 @@ void helper_tlb_flush(CPURISCVState *env)
{
RISCVCPU *cpu = riscv_env_get_cpu(env);
CPUState *cs = CPU(cpu);
- if (env->priv == PRV_S &&
- env->priv_ver >= PRIV_VERSION_1_10_0 &&
- get_field(env->mstatus, MSTATUS_TVM)) {
+ if (!(env->priv >= PRV_S) ||
+ (env->priv == PRV_S &&
+ env->priv_ver >= PRIV_VERSION_1_10_0 &&
+ get_field(env->mstatus, MSTATUS_TVM))) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
tlb_flush(cs);
--
2.21.0
- [Qemu-devel] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode, (continued)
- [Qemu-devel] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 06/29] target/riscv: Merge argument sets for insn32 and insn16, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 03/29] RISC-V: fix single stepping over ret and other branching instructions, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 13/29] linux-user/riscv: Add the CPU type as a comment, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 10/29] target/riscv: Split gen_arith_imm into functional and temp, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 09/29] target/riscv: Split RVC32 and RVC64 insns into separate files, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 05/29] target/riscv: Use --static-decode for decodetree, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 07/29] target/riscv: Merge argument decode for RVC shifti, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 02/29] target/riscv: Do not allow sfence.vma from user mode,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 01/29] SiFive RISC-V GPIO Device, Palmer Dabbelt, 2019/05/25
- Re: [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1, Peter Maydell, 2019/05/28