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[Qemu-devel] [RFC v1 08/23] target/riscv: Add support for background int
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [RFC v1 08/23] target/riscv: Add support for background interrupt setting |
Date: |
Fri, 24 May 2019 16:45:56 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0fdc81f71f..1f466effcf 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -38,12 +38,27 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
+ target_ulong bsstatus_sie = get_field(env->bsstatus, MSTATUS_SIE);
+
target_ulong pending = atomic_read(&env->mip) & env->mie;
- target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M &&
mstatus_mie);
- target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S &&
mstatus_sie);
+ target_ulong hspending = atomic_read(&env->bsip) & env->bsie;
+
+ target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M &&
mstatus_mie);
+ target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S &&
mstatus_sie);
+ target_ulong bsie = env->priv < PRV_S || (env->priv == PRV_S &&
bsstatus_sie);
+
target_ulong irqs = (pending & ~env->mideleg & -mie) |
(pending & env->mideleg & -sie);
+ if (riscv_cpu_virt_enabled(env)) {
+ target_ulong pending_hs_irq = hspending & -bsie;
+
+ if (pending_hs_irq) {
+ riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
+ return ctz64(pending_hs_irq);
+ }
+ }
+
if (irqs) {
return ctz64(irqs); /* since non-zero */
} else {
--
2.21.0
- [Qemu-devel] [RFC v1 19/23] target/riscv: Allow specifying MMU stage, (continued)
- [Qemu-devel] [RFC v1 19/23] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 18/23] target/riscv: Add hfence instructions, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 15/23] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 14/23] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 17/23] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 16/23] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 12/23] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 13/23] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 06/23] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 11/23] target/riscv: Add background register swapping function, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 08/23] target/riscv: Add support for background interrupt setting,
Alistair Francis <=
- [Qemu-devel] [RFC v1 03/23] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 01/23] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 09/23] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 10/23] target/riscv: Add background CSRs accesses, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 07/23] target/riscv: Remove strict perm checking for CSR R/W, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 05/23] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 04/23] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 02/23] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/05/24