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[Qemu-devel] [RFC v1 07/23] target/riscv: Remove strict perm checking fo
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From: |
Alistair Francis |
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Subject: |
[Qemu-devel] [RFC v1 07/23] target/riscv: Remove strict perm checking for CSR R/W |
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Date: |
Fri, 24 May 2019 16:45:53 -0700 |
The privledge check based on the CSR address mask 0x300 doesn't work
when using Hypervisor extensions so remove the check
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/csr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e6d68a9956..c1fcb795cd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -771,9 +771,8 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong
*ret_value,
/* check privileges and return -1 if check fails */
#if !defined(CONFIG_USER_ONLY)
- int csr_priv = get_field(csrno, 0x300);
int read_only = get_field(csrno, 0xC00) == 3;
- if ((write_mask && read_only) || (env->priv < csr_priv)) {
+ if (write_mask && read_only) {
return -1;
}
#endif
--
2.21.0
- [Qemu-devel] [RFC v1 16/23] target/riscv: Add hypvervisor trap support, (continued)
- [Qemu-devel] [RFC v1 16/23] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 12/23] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 13/23] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 06/23] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 11/23] target/riscv: Add background register swapping function, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 08/23] target/riscv: Add support for background interrupt setting, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 03/23] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 01/23] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 09/23] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 10/23] target/riscv: Add background CSRs accesses, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 07/23] target/riscv: Remove strict perm checking for CSR R/W,
Alistair Francis <=
- [Qemu-devel] [RFC v1 05/23] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 04/23] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 02/23] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/05/24