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Re: [Qemu-devel] [PATCH v2 11/27] target/mips: Tidy control flow in mips
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v2 11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault |
Date: |
Thu, 9 May 2019 12:01:18 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 |
On 5/9/19 8:02 AM, Richard Henderson wrote:
> Since the only non-negative TLBRET_* value is TLBRET_MATCH,
> the subsequent test for ret < 0 is useless. Use early return
> to allow subsequent blocks to be unindented.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/mips/helper.c | 54 ++++++++++++++++++++------------------------
> 1 file changed, 24 insertions(+), 30 deletions(-)
>
> diff --git a/target/mips/helper.c b/target/mips/helper.c
> index cc7be7703a..86e622efb8 100644
> --- a/target/mips/helper.c
> +++ b/target/mips/helper.c
> @@ -915,41 +915,35 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr
> address, int size, int rw,
> tlb_set_page(cs, address & TARGET_PAGE_MASK,
> physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
> mmu_idx, TARGET_PAGE_SIZE);
> - ret = 0;
> - } else if (ret < 0)
> -#endif
> - {
> -#if !defined(CONFIG_USER_ONLY)
> + return 0;
> + }
> #if !defined(TARGET_MIPS64)
> - if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
> - /*
> - * Memory reads during hardware page table walking are performed
> - * as if they were kernel-mode load instructions.
> - */
> - int mode = (env->hflags & MIPS_HFLAG_KSU);
> - bool ret_walker;
> - env->hflags &= ~MIPS_HFLAG_KSU;
> - ret_walker = page_table_walk_refill(env, address, rw, mmu_idx);
> - env->hflags |= mode;
> - if (ret_walker) {
> - ret = get_physical_address(env, &physical, &prot,
> - address, rw, access_type,
> mmu_idx);
> - if (ret == TLBRET_MATCH) {
> - tlb_set_page(cs, address & TARGET_PAGE_MASK,
> - physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
> - mmu_idx, TARGET_PAGE_SIZE);
> - ret = 0;
> - return ret;
> - }
> + if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
> + /*
> + * Memory reads during hardware page table walking are performed
> + * as if they were kernel-mode load instructions.
> + */
> + int mode = (env->hflags & MIPS_HFLAG_KSU);
> + bool ret_walker;
> + env->hflags &= ~MIPS_HFLAG_KSU;
> + ret_walker = page_table_walk_refill(env, address, rw, mmu_idx);
> + env->hflags |= mode;
> + if (ret_walker) {
> + ret = get_physical_address(env, &physical, &prot,
> + address, rw, access_type, mmu_idx);
> + if (ret == TLBRET_MATCH) {
> + tlb_set_page(cs, address & TARGET_PAGE_MASK,
> + physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
> + mmu_idx, TARGET_PAGE_SIZE);
> + return 0;
> }
> }
> -#endif
> -#endif
> - raise_mmu_exception(env, address, rw, ret);
> - ret = 1;
> }
> +#endif
> +#endif
>
> - return ret;
> + raise_mmu_exception(env, address, rw, ret);
> + return 1;
> }
>
> #if !defined(CONFIG_USER_ONLY)
>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
- [Qemu-devel] [PATCH v2 03/27] target/arm: Convert to CPUClass::tlb_fill, (continued)
- [Qemu-devel] [PATCH v2 03/27] target/arm: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
- [Qemu-devel] [PATCH v2 04/27] target/cris: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
- [Qemu-devel] [PATCH v2 05/27] target/hppa: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
- [Qemu-devel] [PATCH v2 09/27] target/microblaze: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
- [Qemu-devel] [PATCH v2 06/27] target/i386: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
- [Qemu-devel] [PATCH v2 10/27] target/mips: Pass a valid error to raise_mmu_exception for user-only, Richard Henderson, 2019/05/09
- [Qemu-devel] [PATCH v2 07/27] target/lm32: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
- [Qemu-devel] [PATCH v2 11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault, Richard Henderson, 2019/05/09
- Re: [Qemu-devel] [PATCH v2 11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v2 08/27] target/m68k: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
- [Qemu-devel] [PATCH v2 13/27] target/moxie: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
- [Qemu-devel] [PATCH v2 12/27] target/mips: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
- [Qemu-devel] [PATCH v2 15/27] target/openrisc: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
- [Qemu-devel] [PATCH v2 14/27] target/nios2: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
- [Qemu-devel] [PATCH v2 16/27] target/ppc: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
- [Qemu-devel] [PATCH v2 17/27] target/riscv: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09