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[Qemu-devel] [RFC PATCH 16/17] Add uart reset support in zynq_slcr
From: |
Damien Hedde |
Subject: |
[Qemu-devel] [RFC PATCH 16/17] Add uart reset support in zynq_slcr |
Date: |
Mon, 25 Mar 2019 12:01:59 +0100 |
Add two gpio outputs to control the uart resets.
Signed-off-by: Damien Hedde <address@hidden>
---
hw/misc/zynq_slcr.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index 47f43e1d8d..5aa8f55b45 100644
--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
@@ -96,6 +96,10 @@ REG32(SPI_RST_CTRL, 0x21c)
REG32(CAN_RST_CTRL, 0x220)
REG32(I2C_RST_CTRL, 0x224)
REG32(UART_RST_CTRL, 0x228)
+ FIELD(UART_RST_CTRL, UART0_CPU1X_RST, 0, 1)
+ FIELD(UART_RST_CTRL, UART1_CPU1X_RST, 1, 1)
+ FIELD(UART_RST_CTRL, UART0_REF_RST, 2, 1)
+ FIELD(UART_RST_CTRL, UART1_REF_RST, 3, 1)
REG32(GPIO_RST_CTRL, 0x22c)
REG32(LQSPI_RST_CTRL, 0x230)
REG32(SMC_RST_CTRL, 0x234)
@@ -178,8 +182,14 @@ typedef struct ZynqSLCRState {
MemoryRegion iomem;
uint32_t regs[ZYNQ_SLCR_NUM_REGS];
+
+ qemu_irq uart0_rst;
+ qemu_irq uart1_rst;
} ZynqSLCRState;
+#define ZYNQ_SLCR_REGFIELD_TO_OUT(state, irq, reg, field) \
+ qemu_set_irq((state)->irq, ARRAY_FIELD_EX32((state)->regs, reg, field) !=
0)
+
static void zynq_slcr_reset_init(Object *obj, bool cold)
{
ZynqSLCRState *s = ZYNQ_SLCR(obj);
@@ -276,6 +286,18 @@ static void zynq_slcr_reset_init(Object *obj, bool cold)
s->regs[R_DDRIOB + 12] = 0x00000021;
}
+static void zynq_slcr_compute_uart_reset(ZynqSLCRState *s)
+{
+ ZYNQ_SLCR_REGFIELD_TO_OUT(s, uart0_rst, UART_RST_CTRL, UART0_REF_RST);
+ ZYNQ_SLCR_REGFIELD_TO_OUT(s, uart1_rst, UART_RST_CTRL, UART1_REF_RST);
+}
+
+static void zynq_slcr_reset_hold(Object *obj)
+{
+ ZynqSLCRState *s = ZYNQ_SLCR(obj);
+
+ zynq_slcr_compute_uart_reset(s);
+}
static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
{
@@ -416,6 +438,9 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
break;
+ case R_UART_RST_CTRL:
+ zynq_slcr_compute_uart_reset(s);
+ break;
}
}
@@ -432,6 +457,9 @@ static void zynq_slcr_init(Object *obj)
memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr",
ZYNQ_SLCR_MMIO_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
+
+ qdev_init_gpio_out_named(DEVICE(obj), &s->uart0_rst, "uart0_rst", 1);
+ qdev_init_gpio_out_named(DEVICE(obj), &s->uart1_rst, "uart1_rst", 1);
}
static const VMStateDescription vmstate_zynq_slcr = {
@@ -450,6 +478,7 @@ static void zynq_slcr_class_init(ObjectClass *klass, void
*data)
dc->vmsd = &vmstate_zynq_slcr;
dc->reset_phases.init = zynq_slcr_reset_init;
+ dc->reset_phases.hold = zynq_slcr_reset_hold;
}
static const TypeInfo zynq_slcr_info = {
--
2.21.0
- [Qemu-devel] [RFC PATCH 09/17] global ResetDomain support for legacy reset handlers, (continued)
- [Qemu-devel] [RFC PATCH 09/17] global ResetDomain support for legacy reset handlers, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 10/17] Delete the system ResetDomain at the end of emulation, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 04/17] Add local reset methods in Device class, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 05/17] add vmstate description for device reset state, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 06/17] Add function to control reset with gpio inputs, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 01/17] Create Resettable QOM interface, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 11/17] Put orphan buses in system reset domain, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 12/17] Put default sysbus in system reset domain, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 17/17] Connect the uart reset gpios in the zynq platform, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 14/17] convert cadence_uart to 3-phases reset, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 16/17] Add uart reset support in zynq_slcr,
Damien Hedde <=
- [Qemu-devel] [RFC PATCH 13/17] hw/misc/zynq_slcr: use standard register definition, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 15/17] Convert zynq's slcr to 3-phases reset, Damien Hedde, 2019/03/25
- Re: [Qemu-devel] [RFC 00/17] multi-phase reset mechanism, no-reply, 2019/03/25