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Re: [Qemu-devel] [Qemu-arm] [RFC PATCH 15/17] Convert zynq's slcr to 3-p
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [Qemu-arm] [RFC PATCH 15/17] Convert zynq's slcr to 3-phases reset |
Date: |
Mon, 25 Mar 2019 14:28:33 +0100 |
Hi Damien,
Le lun. 25 mars 2019 12:16, Damien Hedde <address@hidden> a
écrit :
> Change the legacy reset function into the init phase and test the
> resetting flag in register accesses.
>
> Signed-off-by: Damien Hedde <address@hidden>
> ---
> hw/misc/zynq_slcr.c | 14 +++++++++++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
> index baa13d1316..47f43e1d8d 100644
> --- a/hw/misc/zynq_slcr.c
> +++ b/hw/misc/zynq_slcr.c
> @@ -180,9 +180,9 @@ typedef struct ZynqSLCRState {
> uint32_t regs[ZYNQ_SLCR_NUM_REGS];
> } ZynqSLCRState;
>
> -static void zynq_slcr_reset(DeviceState *d)
> +static void zynq_slcr_reset_init(Object *obj, bool cold)
> {
> - ZynqSLCRState *s = ZYNQ_SLCR(d);
> + ZynqSLCRState *s = ZYNQ_SLCR(obj);
> int i;
>
> DB_PRINT("RESET\n");
> @@ -346,6 +346,10 @@ static uint64_t zynq_slcr_read(void *opaque, hwaddr
> offset,
> offset /= 4;
> uint32_t ret = s->regs[offset];
>
> + if (qdev_is_resetting((DeviceState *) opaque)) {
> + return 0;
> + }
> +
> if (!zynq_slcr_check_offset(offset, true)) {
> qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to
> "
> " addr %" HWADDR_PRIx "\n", offset * 4);
> @@ -361,6 +365,10 @@ static void zynq_slcr_write(void *opaque, hwaddr
> offset,
> ZynqSLCRState *s = (ZynqSLCRState *)opaque;
> offset /= 4;
>
> + if (qdev_is_resetting((DeviceState *) opaque)) {
> + return;
>
I wonder if that could be moved to generic parent, as an abstract method.
But then I'm not sure we can use a generic read() return value.
+ }
> +
> DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset *
> 4, val);
>
> if (!zynq_slcr_check_offset(offset, false)) {
> @@ -441,7 +449,7 @@ static void zynq_slcr_class_init(ObjectClass *klass,
> void *data)
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> dc->vmsd = &vmstate_zynq_slcr;
> - dc->reset = zynq_slcr_reset;
> + dc->reset_phases.init = zynq_slcr_reset_init;
> }
>
> static const TypeInfo zynq_slcr_info = {
> --
> 2.21.0
>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
>
- [Qemu-devel] [RFC PATCH 05/17] add vmstate description for device reset state, (continued)
- [Qemu-devel] [RFC PATCH 05/17] add vmstate description for device reset state, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 06/17] Add function to control reset with gpio inputs, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 01/17] Create Resettable QOM interface, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 11/17] Put orphan buses in system reset domain, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 12/17] Put default sysbus in system reset domain, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 17/17] Connect the uart reset gpios in the zynq platform, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 14/17] convert cadence_uart to 3-phases reset, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 16/17] Add uart reset support in zynq_slcr, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 13/17] hw/misc/zynq_slcr: use standard register definition, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 15/17] Convert zynq's slcr to 3-phases reset, Damien Hedde, 2019/03/25
- Re: [Qemu-devel] [Qemu-arm] [RFC PATCH 15/17] Convert zynq's slcr to 3-phases reset,
Philippe Mathieu-Daudé <=
- Re: [Qemu-devel] [RFC 00/17] multi-phase reset mechanism, no-reply, 2019/03/25