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Re: [Qemu-devel] [PATCH 2/2] target/mips: Optimize ILVEV.<B|H|W|D> MSA i
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH 2/2] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions |
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Date: |
Tue, 19 Mar 2019 10:30:02 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 |
On 3/19/19 10:05 AM, Aleksandar Markovic wrote:
> May I ask you to redo this segment of code as Richard
> describe (the exact invocations of TCG functions are in
> a Richard's comment to some of the previous versions of
> this patch). This means redo ILVEV.W handling. Then you
> can compare the performance of two versions, and attach
> the results here. You can also (using -d out-asm or similar
> QEMU options) find out what code is generated for both
> alternatives, and attach the generated code here, maybe
> some folks will find them interesting (I will).
To be fair, this will not affect x86 as a host at the moment.
But the underlying deposit operation is supported by AArch64, PowerPC, and S390
as hosts. There is some support for deposit on x86 as a host within my
tcg_gen_extract2 patch set,
https://lists.gnu.org/archive/html/qemu-devel/2019-03/msg02036.html
which will, in these cases, use rol+shld instead of shr+movq+and+or.
r~