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[Qemu-devel] [PATCH for-4.1 v3 04/17] tcg: Support cross-class moves wit
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH for-4.1 v3 04/17] tcg: Support cross-class moves without instruction support |
Date: |
Tue, 19 Mar 2019 10:21:13 -0700 |
PowerPC Altivec does not support direct moves between vector registers
and general registers. So when tcg_out_mov fails, we can use the
backing memory for the temporary to perform the move.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/tcg.c | 25 ++++++++++++++++++++++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 34ee06564f..b5389ea767 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3369,7 +3369,18 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp
*op)
ots->indirect_base);
}
if (!tcg_out_mov(s, otype, ots->reg, ts->reg)) {
- abort();
+ /* Cross register class move not supported.
+ Store the source register into the destination slot
+ and leave the destination temp as TEMP_VAL_MEM. */
+ assert(!ots->fixed_reg);
+ if (!ts->mem_allocated) {
+ temp_allocate_frame(s, ots);
+ }
+ tcg_out_st(s, ts->type, ts->reg,
+ ots->mem_base->reg, ots->mem_offset);
+ ots->mem_coherent = 1;
+ temp_free_or_dead(s, ots, -1);
+ return;
}
}
ots->val_type = TEMP_VAL_REG;
@@ -3471,7 +3482,11 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
o_preferred_regs, ts->indirect_base);
if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
- abort();
+ /* Cross register class move not supported. Sync the
+ temp back to its slot and load from there. */
+ temp_sync(s, ts, i_allocated_regs, 0, 0);
+ tcg_out_ld(s, ts->type, reg,
+ ts->mem_base->reg, ts->mem_offset);
}
}
new_args[i] = reg;
@@ -3630,7 +3645,11 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
if (ts->reg != reg) {
tcg_reg_free(s, reg, allocated_regs);
if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
- abort();
+ /* Cross register class move not supported. Sync the
+ temp back to its slot and load from there. */
+ temp_sync(s, ts, allocated_regs, 0, 0);
+ tcg_out_ld(s, ts->type, reg,
+ ts->mem_base->reg, ts->mem_offset);
}
}
} else {
--
2.17.2
- [Qemu-devel] [PATCH for-4.1 v3 00/17] tcg/ppc: Add vector opcodes, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 01/17] target/arm: Fill in .opc for cmtst_op, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 02/17] tcg: Assert fixed_reg is read-only, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 04/17] tcg: Support cross-class moves without instruction support,
Richard Henderson <=
- [Qemu-devel] [PATCH for-4.1 v3 03/17] tcg: Return bool success from tcg_out_mov, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 05/17] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 06/17] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 08/17] tcg: Add tcg_out_dupm_vec to the backend interface, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 09/17] tcg/i386: Implement tcg_out_dupm_vec, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 07/17] tcg: Manually expand INDEX_op_dup_vec, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 10/17] tcg/aarch64: Implement tcg_out_dupm_vec, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 11/17] tcg: Add INDEX_op_dup_mem_vec, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 13/17] tcg/ppc: Support vector shift by immediate, Richard Henderson, 2019/03/19