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[Qemu-devel] [PATCH for-4.1 v3 07/17] tcg: Manually expand INDEX_op_dup_
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH for-4.1 v3 07/17] tcg: Manually expand INDEX_op_dup_vec |
Date: |
Tue, 19 Mar 2019 10:21:16 -0700 |
This case is similar to INDEX_op_mov_* in that we need to do
different things depending on the current location of the source.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/aarch64/tcg-target.inc.c | 9 ++--
tcg/i386/tcg-target.inc.c | 8 ++-
tcg/tcg.c | 102 +++++++++++++++++++++++++++++++++++
3 files changed, 109 insertions(+), 10 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 3c786ee581..17e35f2fb6 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -2099,10 +2099,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
- case INDEX_op_mov_vec:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_movi_i64:
- case INDEX_op_dupi_vec:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
g_assert_not_reached();
@@ -2199,9 +2197,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_not_vec:
tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
break;
- case INDEX_op_dup_vec:
- tcg_out_dup_vec(s, type, vece, a0, a1);
- break;
case INDEX_op_shli_vec:
tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));
break;
@@ -2245,6 +2240,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
}
break;
+
+ case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
default:
g_assert_not_reached();
}
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index b8e677e46d..09e2308557 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -2594,10 +2594,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
- case INDEX_op_mov_vec:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_movi_i64:
- case INDEX_op_dupi_vec:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
tcg_abort();
@@ -2786,9 +2784,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_st_vec:
tcg_out_st(s, type, a0, a1, a2);
break;
- case INDEX_op_dup_vec:
- tcg_out_dup_vec(s, type, vece, a0, a1);
- break;
case INDEX_op_x86_shufps_vec:
insn = OPC_SHUFPS;
@@ -2830,6 +2825,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out8(s, a2);
break;
+ case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
default:
g_assert_not_reached();
}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index ca5f3ed5ce..b11b30bbec 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3406,6 +3406,105 @@ static void tcg_reg_alloc_mov(TCGContext *s, const
TCGOp *op)
}
}
+static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
+{
+ const TCGLifeData arg_life = op->life;
+ TCGRegSet dup_out_regs, dup_in_regs;
+ TCGTemp *its, *ots;
+ TCGType itype, vtype;
+ unsigned vece;
+ bool ok;
+
+ ots = arg_temp(op->args[0]);
+ its = arg_temp(op->args[1]);
+
+ /* There should be no fixed vector registers. */
+ tcg_debug_assert(!ots->fixed_reg);
+
+ itype = its->type;
+ vece = TCGOP_VECE(op);
+ vtype = TCGOP_VECL(op) + TCG_TYPE_V64;
+
+ if (its->val_type == TEMP_VAL_CONST) {
+ /* Propagate constant via movi -> dupi. */
+ tcg_target_ulong val = its->val;
+ if (IS_DEAD_ARG(1)) {
+ temp_dead(s, its);
+ }
+ tcg_reg_alloc_do_movi(s, ots, val, arg_life, op->output_pref[0]);
+ return;
+ }
+
+ dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs;
+ dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs;
+
+ /* Allocate the output register now. */
+ if (ots->val_type != TEMP_VAL_REG) {
+ TCGRegSet allocated_regs = s->reserved_regs;
+
+ if (!IS_DEAD_ARG(1) && its->val_type == TEMP_VAL_REG) {
+ /* Make sure to not spill the input register. */
+ tcg_regset_set_reg(allocated_regs, its->reg);
+ }
+ ots->reg = tcg_reg_alloc(s, dup_out_regs, allocated_regs,
+ op->output_pref[0], ots->indirect_base);
+ ots->val_type = TEMP_VAL_REG;
+ ots->mem_coherent = 0;
+ s->reg_to_temp[ots->reg] = ots;
+ }
+
+ switch (its->val_type) {
+ case TEMP_VAL_REG:
+ /*
+ * The dup constriaints must be broad, covering all possible VECE.
+ * However, tcg_op_dup_vec() gets to see the VECE and we allow it
+ * to fail, indicating that extra moves are required for that case.
+ */
+ if (tcg_regset_test_reg(dup_in_regs, its->reg)) {
+ if (tcg_out_dup_vec(s, vtype, vece, ots->reg, its->reg)) {
+ goto done;
+ }
+ /* Try again from memory or a vector input register. */
+ }
+ if (!its->mem_coherent) {
+ /*
+ * The input register is not synced, and so an extra store
+ * would be required to use memory. Attempt an integer-vector
+ * register move first. We do not have a TCGRegSet for this.
+ */
+ if (tcg_out_mov(s, itype, ots->reg, its->reg)) {
+ break;
+ }
+ /* Sync the temp back to its slot and load from there. */
+ temp_sync(s, its, s->reserved_regs, 0, 0);
+ }
+ /* fall through */
+
+ case TEMP_VAL_MEM:
+ /* TODO: dup from memory */
+ tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ /* We now have a vector input register, so dup must succeed. */
+ ok = tcg_out_dup_vec(s, vtype, vece, ots->reg, ots->reg);
+ tcg_debug_assert(ok);
+
+ done:
+ if (IS_DEAD_ARG(1)) {
+ temp_dead(s, its);
+ }
+ if (NEED_SYNC_ARG(0)) {
+ temp_sync(s, ots, s->reserved_regs, 0, 0);
+ }
+ if (IS_DEAD_ARG(0)) {
+ temp_dead(s, ots);
+ }
+}
+
static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
{
const TCGLifeData arg_life = op->life;
@@ -3974,6 +4073,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
case INDEX_op_dupi_vec:
tcg_reg_alloc_movi(s, op);
break;
+ case INDEX_op_dup_vec:
+ tcg_reg_alloc_dup(s, op);
+ break;
case INDEX_op_insn_start:
if (num_insns >= 0) {
size_t off = tcg_current_code_size(s);
--
2.17.2
- [Qemu-devel] [PATCH for-4.1 v3 00/17] tcg/ppc: Add vector opcodes, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 01/17] target/arm: Fill in .opc for cmtst_op, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 02/17] tcg: Assert fixed_reg is read-only, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 04/17] tcg: Support cross-class moves without instruction support, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 03/17] tcg: Return bool success from tcg_out_mov, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 05/17] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 06/17] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 08/17] tcg: Add tcg_out_dupm_vec to the backend interface, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 09/17] tcg/i386: Implement tcg_out_dupm_vec, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 07/17] tcg: Manually expand INDEX_op_dup_vec,
Richard Henderson <=
- [Qemu-devel] [PATCH for-4.1 v3 10/17] tcg/aarch64: Implement tcg_out_dupm_vec, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 11/17] tcg: Add INDEX_op_dup_mem_vec, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 13/17] tcg/ppc: Support vector shift by immediate, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 14/17] tcg/ppc: Support vector multiply, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 15/17] tcg/ppc: Update vector support to v2.06, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 16/17] tcg/ppc: Update vector support to v2.07, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 12/17] tcg/ppc: Initial backend support for Altivec, Richard Henderson, 2019/03/19
- [Qemu-devel] [PATCH for-4.1 v3 17/17] tcg/ppc: Update vector support to v3.00, Richard Henderson, 2019/03/19
- Re: [Qemu-devel] [PATCH for-4.1 v3 00/17] tcg/ppc: Add vector opcodes, no-reply, 2019/03/19
- Re: [Qemu-devel] [PATCH for-4.1 v3 00/17] tcg/ppc: Add vector opcodes, Mark Cave-Ayland, 2019/03/20