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[Qemu-devel] [PULL 07/19] RISC-V: Replace __builtin_popcount with ctpop8
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 07/19] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC |
Date: |
Tue, 19 Mar 2019 05:47:51 -0700 |
From: Michael Clark <address@hidden>
The mode variable only uses the lower 4-bits (M,H,S,U) so
replace the GCC specific __builtin_popcount with ctpop8.
Cc: Palmer Dabbelt <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_plic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index d12ec3fc9a54..b859f919a71d 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -383,7 +383,7 @@ static void parse_hart_config(SiFivePLICState *plic)
p = plic->hart_config;
while ((c = *p++)) {
if (c == ',') {
- addrid += __builtin_popcount(modes);
+ addrid += ctpop8(modes);
modes = 0;
hartid++;
} else {
@@ -397,7 +397,7 @@ static void parse_hart_config(SiFivePLICState *plic)
}
}
if (modes) {
- addrid += __builtin_popcount(modes);
+ addrid += ctpop8(modes);
}
hartid++;
--
2.19.2
- [Qemu-devel] [PULL 18/19] riscv: sifive_uart: Generate TX interrupt, (continued)
- [Qemu-devel] [PULL 18/19] riscv: sifive_uart: Generate TX interrupt, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 17/19] target/riscv: Remove unused struct, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 16/19] riscv: sifive_u: Allow up to 4 CPUs to be created, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 12/19] RISC-V: Change local interrupts from edge to level, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 15/19] RISC-V: Update load reservation comment in do_interrupt, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 14/19] RISC-V: Convert trap debugging to trace events, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 13/19] RISC-V: Add support for vectored interrupts, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 11/19] RISC-V: linux-user support for RVE ABI, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 09/19] RISC-V: Remove unnecessary disassembler constraints, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 08/19] RISC-V: Allow interrupt controllers to claim interrupts, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 07/19] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 05/19] RISC-V: Add hooks to use the gdb xml files., Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 03/19] RISC-V: Fixes to CSR_* register macros., Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 06/19] riscv: pmp: Log pmp access errors as guest errors, Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 04/19] RISC-V: Add debug support for accessing CSRs., Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 02/19] RISC-V: Add 64-bit gdb xml files., Palmer Dabbelt, 2019/03/19
- [Qemu-devel] [PULL 01/19] RISC-V: Add 32-bit gdb xml files., Palmer Dabbelt, 2019/03/19
- Re: [Qemu-devel] [PULL] RISC-V Patches for 4.0-rc0, Part 2, Peter Maydell, 2019/03/19