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Re: [Qemu-devel] [PATCH 07/11] target/hppa: fix b,gate instruction
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 07/11] target/hppa: fix b,gate instruction |
Date: |
Mon, 11 Mar 2019 18:17:44 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 |
On 3/11/19 12:15 PM, Sven Schnelle wrote:
> b,gate does GR[t] ← cat(GR[t]{0..29},IAOQ_Front{30..31});
> instead of saving the link address to register t.
>
Quite right. Silly mistake.
> #ifndef CONFIG_USER_ONLY
> + TCGv_reg tmp;
> if (ctx->tb_flags & PSW_C) {
> CPUHPPAState *env = ctx->cs->env_ptr;
> int type = hppa_artype_for_page(env, ctx->base.pc_next);
> @@ -3480,12 +3481,13 @@ static bool trans_b_gate(DisasContext *ctx,
> arg_b_gate *a)
> if (type >= 4 && type - 4 < ctx->privilege) {
> dest = deposit32(dest, 0, 2, type - 4);
> }
> + tmp = dest_gpr(ctx, a->l);
> + tcg_gen_deposit_reg(tmp, tmp, cpu_iaoq_f, 0, 2);
> } else {
> dest &= -4; /* priv = 0 */
> }
> #endif
> -
> - return do_dbranch(ctx, dest, a->l, a->n);
> + return do_dbranch(ctx, dest, 0, a->n);
This change needs to be outside the CONFIG_USER_ONLY. It needs to handle
nullification (which was previously all handled in do_dbranch). I'm thinking
of something like the following.
r~
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index f3e78b8e22..6ac196804b 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3446,6 +3446,8 @@ static bool trans_b_gate
{
target_ureg dest = iaoq_dest(ctx, a->disp);
+ nullify_over(ctx);
+
/* Make sure the caller hasn't done something weird with the queue.
* ??? This is not quite the same as the PSW[B] bit, which would be
* expensive to track. Real hardware will trap for
@@ -3483,7 +3485,16 @@ static bool trans_b_gate
}
#endif
- return do_dbranch(ctx, dest, a->l, a->n);
+ if (a->l) {
+ TCGv_reg tmp = dest_gpr(ctx, a->l);
+ if (ctx->privilege < 3) {
+ tcg_gen_andi_reg(tmp, tmp, -4);
+ }
+ tcg_gen_ori_reg(tmp, tmp, ctx->privilege);
+ save_gpr(ctx, a->l, tmp);
+ }
+
+ return do_dbranch(ctx, dest, 0, a->n);
}
static bool trans_blr(DisasContext *ctx, arg_blr *a)
- [Qemu-devel] [PATCH 00/11] target/hppa patches, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 11/11] target/hppa: call eval_interrupt() after ssm, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 09/11] target/hppa: add TLB protection id check, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 06/11] target/hppa: ignore DIAG opcode, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 10/11] target/hppa: exit TB if either Data or Instruction TLB changes, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 07/11] target/hppa: fix b,gate instruction, Sven Schnelle, 2019/03/11
- Re: [Qemu-devel] [PATCH 07/11] target/hppa: fix b,gate instruction,
Richard Henderson <=
- [Qemu-devel] [PATCH 05/11] target/hppa: remove PSW I/R/Q bit check, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 01/11] target/hppa: fix overwriting source reg in addb, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 02/11] target/hppa: fix TLB handling for page 0, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 03/11] target/hppa: report ITLB_EXCP_MISS for ITLB misses, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 04/11] target/hppa: add TLB trace events, Sven Schnelle, 2019/03/11