[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 15/60] target/ppc: Refactor kvm_handle_debug
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 15/60] target/ppc: Refactor kvm_handle_debug |
Date: |
Sun, 10 Mar 2019 19:26:18 +1100 |
From: Fabiano Rosas <address@hidden>
There are four scenarios being handled in this function:
- single stepping
- hardware breakpoints
- software breakpoints
- fallback (no debug supported)
A future patch will add code to handle specific single step and
software breakpoints cases so let's split each scenario into its own
function now to avoid hurting readability.
Signed-off-by: Fabiano Rosas <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/kvm.c | 86 ++++++++++++++++++++++++++++--------------------
1 file changed, 50 insertions(+), 36 deletions(-)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 996b08a1d3..4e3f1e4b78 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -1624,52 +1624,66 @@ static int kvm_handle_hw_breakpoint(CPUState *cs,
return handle;
}
+static int kvm_handle_singlestep(void)
+{
+ return 1;
+}
+
+static int kvm_handle_sw_breakpoint(void)
+{
+ return 1;
+}
+
static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
- int handle = 0;
if (cs->singlestep_enabled) {
- handle = 1;
- } else if (arch_info->status) {
- handle = kvm_handle_hw_breakpoint(cs, arch_info);
- } else if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
- handle = 1;
- } else {
- /* QEMU is not able to handle debug exception, so inject
- * program exception to guest;
- * Yes program exception NOT debug exception !!
- * When QEMU is using debug resources then debug exception must
- * be always set. To achieve this we set MSR_DE and also set
- * MSRP_DEP so guest cannot change MSR_DE.
- * When emulating debug resource for guest we want guest
- * to control MSR_DE (enable/disable debug interrupt on need).
- * Supporting both configurations are NOT possible.
- * So the result is that we cannot share debug resources
- * between QEMU and Guest on BOOKE architecture.
- * In the current design QEMU gets the priority over guest,
- * this means that if QEMU is using debug resources then guest
- * cannot use them;
- * For software breakpoint QEMU uses a privileged instruction;
- * So there cannot be any reason that we are here for guest
- * set debug exception, only possibility is guest executed a
- * privileged / illegal instruction and that's why we are
- * injecting a program interrupt.
- */
+ return kvm_handle_singlestep();
+ }
- cpu_synchronize_state(cs);
- /* env->nip is PC, so increment this by 4 to use
- * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
- */
- env->nip += 4;
- cs->exception_index = POWERPC_EXCP_PROGRAM;
- env->error_code = POWERPC_EXCP_INVAL;
- ppc_cpu_do_interrupt(cs);
+ if (arch_info->status) {
+ return kvm_handle_hw_breakpoint(cs, arch_info);
}
- return handle;
+ if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
+ return kvm_handle_sw_breakpoint();
+ }
+
+ /*
+ * QEMU is not able to handle debug exception, so inject
+ * program exception to guest;
+ * Yes program exception NOT debug exception !!
+ * When QEMU is using debug resources then debug exception must
+ * be always set. To achieve this we set MSR_DE and also set
+ * MSRP_DEP so guest cannot change MSR_DE.
+ * When emulating debug resource for guest we want guest
+ * to control MSR_DE (enable/disable debug interrupt on need).
+ * Supporting both configurations are NOT possible.
+ * So the result is that we cannot share debug resources
+ * between QEMU and Guest on BOOKE architecture.
+ * In the current design QEMU gets the priority over guest,
+ * this means that if QEMU is using debug resources then guest
+ * cannot use them;
+ * For software breakpoint QEMU uses a privileged instruction;
+ * So there cannot be any reason that we are here for guest
+ * set debug exception, only possibility is guest executed a
+ * privileged / illegal instruction and that's why we are
+ * injecting a program interrupt.
+ */
+ cpu_synchronize_state(cs);
+ /*
+ * env->nip is PC, so increment this by 4 to use
+ * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
+ */
+ env->nip += 4;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_INVAL;
+ ppc_cpu_do_interrupt(cs);
+
+ return 0;
}
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
--
2.20.1
- [Qemu-devel] [PULL 12/60] target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type, (continued)
- [Qemu-devel] [PULL 12/60] target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 11/60] target/ppc/tcg: make spapr_caps apply cap-[cfpc/sbbc/ibs] non-fatal for tcg, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 10/60] target/ppc/spapr: Add SPAPR_CAP_CCF_ASSIST, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 18/60] spapr: Force SPAPR_MEMORY_BLOCK_SIZE to be a hwaddr (64-bit), David Gibson, 2019/03/10
- [Qemu-devel] [PULL 19/60] target/ppc/spapr: Enable H_PAGE_INIT in-kernel handling, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 17/60] target/ppc/spapr: Clear partition table entry when allocating hash table, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 14/60] target/ppc: Move handling of hardware breakpoints to a separate function, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 29/60] ppc/xive: activate HV support, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 21/60] ppc/xive: hardwire the Physical CAM line of the thread context, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 06/60] target/ppc: Implement large decrementer support for TCG, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 15/60] target/ppc: Refactor kvm_handle_debug,
David Gibson <=
- [Qemu-devel] [PULL 22/60] ppc: externalize ppc_get_vcpu_by_pir(), David Gibson, 2019/03/10
- [Qemu-devel] [PULL 25/60] ppc/pnv: change the CPU machine_data presenter type to Object *, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 20/60] PPC: E500: Add FSL I2C controller and integrate RTC with it, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 32/60] ppc/pnv: psi: add a reset handler, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 30/60] ppc/pnv: fix logging primitives using Ox, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 28/60] ppc/pnv: introduce a new pic_print_info() operation to the chip model, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 31/60] ppc/pnv: psi: add a PSIHB_REG macro, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 23/60] ppc/xive: export the TIMA memory accessors, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 41/60] mac_oldworld: use node name instead of alias name for hd device in FWPathProvider, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 24/60] ppc/pnv: export the xive_router_notify() routine, David Gibson, 2019/03/10