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[Qemu-devel] [PATCH v2 5/7] target/ppc: improve avr64_offset() and use i
From: |
Mark Cave-Ayland |
Subject: |
[Qemu-devel] [PATCH v2 5/7] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64() |
Date: |
Thu, 7 Mar 2019 18:05:18 +0000 |
By using the VsrD macro in avr64_offset() the same offset calculation can be
used regardless of the host endian. This allows get_avr64() and set_avr64() to
be simplified accordingly.
Signed-off-by: Mark Cave-Ayland <address@hidden>
---
target/ppc/cpu.h | 5 +++++
target/ppc/translate.c | 16 ++--------------
target/ppc/translate/vmx-impl.inc.c | 5 -----
3 files changed, 7 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 2a2792306f..aebb6c01ee 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2608,6 +2608,11 @@ static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env,
int i)
return (uint64_t *)((uintptr_t)env + vsrl_offset(i));
}
+static inline long avr64_offset(int i, bool high)
+{
+ return offsetof(CPUPPCState, vsr[32 + i].VsrD(high ? 0 : 1));
+}
+
static inline int avr_full_offset(int i)
{
return vsr_full_offset(i + 32);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3b1992faf1..a6cff20daf 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6687,24 +6687,12 @@ static inline void set_fpr(int regno, TCGv_i64 src)
static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
{
-#ifdef HOST_WORDS_BIGENDIAN
- tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState,
- vsr[32 + regno].u64[(high ? 0 :
1)]));
-#else
- tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState,
- vsr[32 + regno].u64[(high ? 1 :
0)]));
-#endif
+ tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high));
}
static inline void set_avr64(int regno, TCGv_i64 src, bool high)
{
-#ifdef HOST_WORDS_BIGENDIAN
- tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState,
- vsr[32 + regno].u64[(high ? 0 :
1)]));
-#else
- tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState,
- vsr[32 + regno].u64[(high ? 1 :
0)]));
-#endif
+ tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
}
#include "translate/fp-impl.inc.c"
diff --git a/target/ppc/translate/vmx-impl.inc.c
b/target/ppc/translate/vmx-impl.inc.c
index 4e5d0bc0e0..eb10c533ca 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -14,11 +14,6 @@ static inline TCGv_ptr gen_avr_ptr(int reg)
return r;
}
-static inline long avr64_offset(int reg, bool high)
-{
- return offsetof(CPUPPCState, vsr[32 + reg].u64[(high ? 0 : 1)]);
-}
-
#define GEN_VR_LDX(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx)
\
{ \
--
2.11.0
- [Qemu-devel] [PATCH v2 0/7] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, Mark Cave-Ayland, 2019/03/07
- [Qemu-devel] [PATCH v2 2/7] target/ppc: introduce single vsrl_offset() function, Mark Cave-Ayland, 2019/03/07
- [Qemu-devel] [PATCH v2 5/7] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64(),
Mark Cave-Ayland <=
- [Qemu-devel] [PATCH v2 3/7] target/ppc: move Vsr* macros from internal.h to cpu.h, Mark Cave-Ayland, 2019/03/07
- [Qemu-devel] [PATCH v2 7/7] target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}(), Mark Cave-Ayland, 2019/03/07
- [Qemu-devel] [PATCH v2 1/7] target/ppc: introduce single fpr_offset() function, Mark Cave-Ayland, 2019/03/07
- [Qemu-devel] [PATCH v2 4/7] target/ppc: introduce avr_full_offset() function, Mark Cave-Ayland, 2019/03/07