Re: [Qemu-devel] [PATCH] target/mips: Fix minor bug in FPU

[Alex Bennée]

Mateja Marjanovic <address@hidden> writes:

> From: Mateja Marjanovic <address@hidden>
>
> Wrong type of NaN was generated by maddf and msubf insturctions
> when the arguments were inf, zero, nan or zero, inf, nan
> respectively.
>
> Signed-off-by: Mateja Marjanovic <address@hidden>
> ---
>  fpu/softfloat-specialize.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
> index 16c0bcb..647bfbc 100644
> --- a/fpu/softfloat-specialize.h
> +++ b/fpu/softfloat-specialize.h
> @@ -500,7 +500,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass 
> b_cls, FloatClass c_cls,
>       */
>      if (infzero) {
>          float_raise(float_flag_invalid, status);
> -        return 3;
> +        return 2;

Hi,

This changes the behaviour documented above which says:

    /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns
     * the default NaN
     */

So if the behaviour is incorrect please update the comment as well.
Bonus points for a reference to the canonical reference document that
describes this.

--
Alex Bennée