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[Qemu-devel] [PATCH v4 17/22] target/arm: Set PSTATE.TCO on exception en
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 17/22] target/arm: Set PSTATE.TCO on exception entry |
Date: |
Thu, 7 Mar 2019 09:04:35 -0800 |
R0085 specifies that exception handlers begin with tag checks overridden.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
v2: Only set if MTE feature present.
---
target/arm/helper.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c8773a5528..a529d30700 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9628,6 +9628,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
target_ulong addr = env->cp15.vbar_el[new_el];
unsigned int new_mode = aarch64_pstate_mode(new_el, true);
unsigned int cur_el = arm_current_el(env);
+ unsigned int new_pstate;
/*
* Note that new_el can never be 0. If cur_el is 0, then
@@ -9721,7 +9722,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
env->elr_el[new_el]);
- pstate_write(env, PSTATE_DAIF | new_mode);
+ new_pstate = new_mode | PSTATE_DAIF;
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ new_pstate |= PSTATE_TCO;
+ }
+ pstate_write(env, new_pstate);
env->aarch64 = 1;
aarch64_restore_sp(env, new_el);
--
2.17.2
- [Qemu-devel] [PATCH v4 09/22] target/arm: Implement the SUBP instruction, (continued)
- [Qemu-devel] [PATCH v4 09/22] target/arm: Implement the SUBP instruction, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 03/22] target/arm: Add MTE system registers, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 08/22] target/arm: Implement the GMI instruction, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 06/22] target/arm: Implement the IRG instruction, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 21/22] target/arm: Add allocation tag storage for system mode, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 20/22] target/arm: Create a TLB entry for tag physical address space, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 15/22] target/arm: Clean address for DC ZVA, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 19/22] target/arm: Create tagged ram when MTE is enabled, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 17/22] target/arm: Set PSTATE.TCO on exception entry,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 22/22] target/arm: Enable MTE, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 18/22] target/arm: Cache the Tagged bit for a page in MemTxAttrs, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 14/22] target/arm: Implement the access tag cache flushes, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 11/22] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 16/22] target/arm: Implement data cache set allocation tags, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 13/22] target/arm: Implement the LDGM and STGM instructions, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 12/22] target/arm: Implement the STGP instruction, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH v4 10/22] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY, Richard Henderson, 2019/03/07
- Re: [Qemu-devel] [PATCH v4 00/22] target/arm: Implement ARMv8.5-MemTag, system mode, no-reply, 2019/03/07
- Re: [Qemu-devel] [PATCH v4 00/22] target/arm: Implement ARMv8.5-MemTag, system mode, no-reply, 2019/03/08