[Qemu-devel] [PATCH 4/5] hw/mips/malta: Only accept 'monitor' pflash of 4MiB

[Philippe Mathieu-Daudé]

The Malta 'mother' board can use various 'daughter' core cards [1].
QEMU only models the CoreLV card.

The CoreLV card provides [2] a Galileo GT64120 as North bridge,
connecting the CPU via the 'CBUS'. The CBUS also connects a 'Monitor
flash' memory and maps it to the CPU RESET vector.
The Monitor flash size is exactly 4 MiB.
Refuse Monitor pflash of different size.

[1] https://www.linux-mips.org/wiki/MIPS_Malta#Core_cards
[2] "Malta User's Manual"  rev. 01.05 (MIPS Technologies doc number: MD00048)

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
 hw/mips/mips_malta.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 396645b1a9..04788ff50a 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1267,6 +1267,11 @@ void mips_malta_init(MachineState *machine)
     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
     if (dinfo) {
         pflash_blk = blk_by_legacy_dinfo(dinfo);
+
+        if (blk_getlength(pflash_blk) != FLASH_SIZE) {
+                error_report("Malta CoreLV card expects a bios of 4MB");
+                exit(1);
+        }
 #ifdef DEBUG_BOARD_INIT
         printf("Register parallel flash %d size " TARGET_FMT_lx " at "
                "addr %08llx '%s'\n",
-- 
2.20.1