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[Qemu-devel] [PULL 15/27] target/arm: Rely on optimization within tcg_ge
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/27] target/arm: Rely on optimization within tcg_gen_gvec_or |
Date: |
Thu, 14 Feb 2019 19:05:51 +0000 |
From: Richard Henderson <address@hidden>
Since we're now handling a == b generically, we no longer need
to do it by hand within target/arm/.
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 6 +-----
target/arm/translate-sve.c | 6 +-----
target/arm/translate.c | 12 +++---------
3 files changed, 5 insertions(+), 19 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2f849a6951d..08c13484cd7 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10652,11 +10652,7 @@ static void disas_simd_3same_logic(DisasContext *s,
uint32_t insn)
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0);
return;
case 2: /* ORR */
- if (rn == rm) { /* MOV */
- gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_mov, 0);
- } else {
- gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0);
- }
+ gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0);
return;
case 3: /* ORN */
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0);
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index b15b615ceb3..3a2eb515664 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -280,11 +280,7 @@ static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
{
- if (a->rn == a->rm) { /* MOV */
- return do_mov_z(s, a->rd, a->rn);
- } else {
- return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
- }
+ return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
}
static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index eb258958768..eaa6e297384 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6294,15 +6294,9 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
break;
- case 2:
- if (rn == rm) {
- /* VMOV */
- tcg_gen_gvec_mov(0, rd_ofs, rn_ofs, vec_size, vec_size);
- } else {
- /* VORR */
- tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
- vec_size, vec_size);
- }
+ case 2: /* VORR */
+ tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
+ vec_size, vec_size);
break;
case 3: /* VORN */
tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs,
--
2.20.1
- [Qemu-devel] [PULL 02/27] target/arm: Implement HACR_EL2, (continued)
- [Qemu-devel] [PULL 02/27] target/arm: Implement HACR_EL2, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 03/27] target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 04/27] target/arm: Force result size into dp after operation, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 05/27] target/arm: Restructure disas_fp_int_conv, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 06/27] target/arm: relax permission checks for HWCAP_CPUID registers, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 07/27] target/arm: expose CPUID registers to userspace, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 08/27] target/arm: expose MPIDR_EL1 to userspace, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 09/27] target/arm: expose remaining CPUID registers as RAZ, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 10/27] linux-user/elfload: enable HWCAP_CPUID for AArch64, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 12/27] MAINTAINERS: Remove Peter Crosthwaite from various entries, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 15/27] target/arm: Rely on optimization within tcg_gen_gvec_or,
Peter Maydell <=
- [Qemu-devel] [PULL 19/27] target/arm: Remove neon min/max helpers, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 14/27] hw/arm/armsse: Fix miswiring of expansion IRQs, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 13/27] hw/intc/armv7m_nvic: Allow byte accesses to SHPR1, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 11/27] arm: Allow system registers for KVM guests to be changed by QEMU code, Peter Maydell, 2019/02/14